Hi All,
I am trying to reset the CPU in the middle of a debugging session. I am using Application Interrupt and Reset control register by setting the SysResetReq bit in the SCB block. (this preserves the current debugging session also).
However, as I am using ASM its a bit cumbersome. This is the code snippet I am trying to use..
AIRCR EQU 0xE000ED0C.
.
Any feedback/input help will always be appreciated.
Thanks!!
BR,
\ksnf3000
I am trying something like this but I dont think its working.
The SYS_NVFLAGSSET, as I understand, is a general purpose flag register. I am trying to set its flag so that on reset it checks the value and comes out of this reset loop. Not sure if this is right.
\Kashif
Yeah got it!! Thanks!
Also, could you provide your input on my 2nd query? "So, now is there a way I can come out of this reset/startup? I mean I want that the CPU only resets once and then resumes say from the LDR R5 instruction. Any ideas on how can this be achieved?" Means that I want this reset to happen only ONCE everytime the code runs and then come out of this reset loop and continue working.
Hi Kashif
__ " It works if I add a small segment of code like a delay Loop. Don't know why!!"
delay is to Wait until reset happen (How many cycles is device-specific);
__ after a reset ,program execution always start at Reset _Handler
Ali
Hi Ali,
It works if I add a small segment of code like a delay loop. Don't know why!!
So, now is there a way I can come out of this reset/startup? I mean I want that the CPU only resets once and then resumes say from the LDR R5 instruction. Any ideas on how can this be achieved?
Thanks!! but sadly, I cant see this behavior happening in my code. I even commented all my code and used exactly the part which is mentioned in your code but still no results.
Is it due to the different set of registers I maybe using? I am using R10 to load the AIRCR value and R9 for storing the 0x05FA0001?
Hi
-AIRCR : (Register writes must write 0x05FA otherwise the write is ignored ,On reads Returns 0xFA05 ).
-After the STR instruction, the Debugger jumps back to the Reset_Handler.
On using the value provided by you (0x05fa0001), I noticed something interesting. After the STR instruction, the debugger jumps back to the LDR instruction of loading the AIRCR address (LDR R0,=0xE000ED0C) and clears the R9 and R10 registers.
Is this a reset? looks like one,because its in a loop but I don't exactly get what is happening.
Thanks!
Hi Ali/All,
I tried the same thing. However, I used registers R9 and R10. But it fails to write to them as you can see in the snapshot below. and at the beginning of the code I used AIRCR EQU 0xE000ED0C
Also, I used the value 0xfa050001, which I see is different in representation from yours.
Please advice.
LDR R0,=0xE000ED0C
LDR R1,=0x05fa0001
STR R1,[R0]
I hope this helps
Thanks Stevens. Could you/anyone possibly let me know how to set this specific bit using ASM?
If you only want to reset CPU (excluding its debug components), possibly you can try to set VECTRESET bit in Application Interrupt and Reset Control Register.
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