Hi,
I trying to build the peripheral around Cortex-M0 IP core thorugh AHB-lite system. Right now I have to integrate Cortex-M0 with the DDR2 SRAM (1Gb) through AHB lite.
I searched on internet which shows interfacing only through core generator (MIG). Is there a way I can use Xilinx core generator to interface through AHB lite system.
I am using Atlys Xilinx Spartan 6.
I also have some example SoC design which interface 128Mb SRAM to Cortex-M0 though AHB lite for Nexsys 3 board . But the Board I am using has DDR2 RAM.
Thanks
First of all, why do you want to use the DDR2 memory instead of SRAM inside the FPGA?
You can implement SRAM inside the FPGA for program and data easily.
(See http://community.arm.com/docs/DOC-8378)
Also, DDR2 access has latency cycles which means you get lower system performance.
If you definitively need DDR2 then there are plenty of commerical DDR2 memory controllers available.
Just google "DDR2 AHB verilog" returns quite a few products.
If you want free designs I am not aware of anything suiteable. There are some DDR2 memory controller Verilog projects on the web but not AHB based.
(But I didn't try very hard to look for it).
regards,
Joseph
Sir,
The project I am working on require large storage of data, secondly the board(Atlys board) I am using has 128MB of DDR2 SDRAM. I will check how much memory I can create inside FPGA. I also searched for memory controller but could not find which integrate using AHB Should I go for designing memory controller by myself??
Another thing is that I have to integrate ADC as a peripheral to cortex M0 and my Board does not have any ADC. What can be done for integrating ADC with it?
Can we find ADC IP core for it ? But Analog part of ADC how can that be mapped on FPGA??
You can try modify some of the free DDR2 memory controllers on the web to switch it to use AHB interface. And of course you can create your own DDR2 controller but that would be quite a lot of work.
You cannot design ADC in classic Xilinx FPGA. There are some new products available which support analog components including ADC:
- Xilinx Artix 7, Zynq-7000, Kintex-7 and Virtex-7 (Analog Mixed Signal)
- Cypress PSoC4 (PSoC® 4 - Cypress) and PSoC5LP
- MicroSemi SmartFusion (www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion)
... maybe some more from other vendors
If you have already got you FPGA board, then maybe you can try adding ADC using a parallel or SPI interface.
(If using SPI interface you need a SPI interface module.)
If you haven't brough you board yet, maybe you should consider:
1) ARM Cortex-M Prototyping System (Cortex-M Prototyping System - ARM)
- 8MB of ZBT SSRAM + 16MB PSRAM
- with various system interface IP (Verilog module) for memory
- SPI interface for external SPI ADC
2) SmartFusion Development Kit
http://www.microsemi.com/products/fpga-soc/design-resources/dev-kits/smartfusion/smartfusion-development-kit#overview
- 2MB external SRAM+16MB flash+16MB PSRAM
- System IP included in Libero IDE (please double check with their sales team first. From my understanding the IP is stored in the IDE in protected form so you cannot change or view the source code).
i) I was wondering how much on chip memory I can get on spatran 6 FPGA with cortex M0 running in it.
ii) Making DDR2 controller would be big task.
iii) I was trying for the CMSDK( cortex M system design Kit). Is there module available like AHB to SRAM and for other peripheral? Is there any licencing fee for getting it?
iv) I have zynq 7000 board available in my lab. I checked It has it own cortexA9 processor and XADC as well. But changing board would take time.
i) See Xilinx datasheet
http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf
However, please note that even LX45 got 2088Kbits (256Kbytes) of memory, it doesn't necessary means you can fully utilize that in your project.
(e.g. place and routing limitations)
You need to do some homework to test it yourself.
ii) Yes, that's why it is not free.
iii) The full CMSDK product require licensing. But if you buy the Cortex-M Prototyping System (FPGA board), it included a subset of the CMSDK include AHB to external SRAM interface (also work with PSRAM).
iv) They have application note:
http://www.wiki.xilinx.com/Zynq+XADC+to+PS+App+Note