Hi,
I trying to build the peripheral around Cortex-M0 IP core thorugh AHB-lite system. Right now I have to integrate Cortex-M0 with the DDR2 SRAM (1Gb) through AHB lite.
I searched on internet which shows interfacing only through core generator (MIG). Is there a way I can use Xilinx core generator to interface through AHB lite system.
I am using Atlys Xilinx Spartan 6.
I also have some example SoC design which interface 128Mb SRAM to Cortex-M0 though AHB lite for Nexsys 3 board . But the Board I am using has DDR2 RAM.
Thanks
Hi Vivek
It is good to see you getting in touch with ARM University Program.
We are currently offering a variety of teaching materials, however most of them are only available for educators (professors, lectures etc). You are welcome to suggest your supervisor or professor to adopt ARM-based teaching material to set up courses or labs.
To do that, they simply need to go to:
www.arm.com/university
click "educator", and then "Register for ARM University Program Today"
We will also have some materials open for students shortly, you could follow the same steps but select "student" rather than "educator".
For any enquiry please contact: university@arm.com
Thank you
Sean Hong
ARM University Program
Thanks Sean,
I will surely inform my professor about the SoC lab and course material.