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Design Start ARM Cortex-M0

Hi,

I trying to build the peripheral around Cortex-M0 IP core thorugh AHB-lite system. Right now I have to integrate Cortex-M0 with the DDR2 SRAM (1Gb) through AHB lite.

I searched on  internet which shows interfacing only through core generator (MIG). Is there a way I can use  Xilinx core generator to interface through AHB lite system.

I am using  Atlys Xilinx Spartan 6.


I also have some  example SoC design which interface 128Mb SRAM  to Cortex-M0 though AHB lite for Nexsys 3 board . But the Board I am using  has DDR2 RAM.


Thanks

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  • soc1.jpgsoc2.png

    Hi,

    I have changed count value as well to 20(14hex). But still i think it is branching to uninitialized memory location. I am also sending you the memory initialized after hex file generation. Still I could not see the pattern on data bus. checked in disassembly  window putting break point  after each line it is working but on on LSIM. I do not know the reason

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  • soc1.jpgsoc2.png

    Hi,

    I have changed count value as well to 20(14hex). But still i think it is branching to uninitialized memory location. I am also sending you the memory initialized after hex file generation. Still I could not see the pattern on data bus. checked in disassembly  window putting break point  after each line it is working but on on LSIM. I do not know the reason

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