Hi,
I trying to build the peripheral around Cortex-M0 IP core thorugh AHB-lite system. Right now I have to integrate Cortex-M0 with the DDR2 SRAM (1Gb) through AHB lite.
I searched on internet which shows interfacing only through core generator (MIG). Is there a way I can use Xilinx core generator to interface through AHB lite system.
I am using Atlys Xilinx Spartan 6.
I also have some example SoC design which interface 128Mb SRAM to Cortex-M0 though AHB lite for Nexsys 3 board . But the Board I am using has DDR2 RAM.
Thanks
1) I have already implemented the above paper for flashing LED under Software control. When Implemented it I saw all LED giving expected output and also glitch which paper mentioned.
2) I was trying for Examlpe ARM _SOC1 and other Mem_control etc. Those example I could not do on board. I run simulation but could not interpret the output.
3) Yeah AHB2MEM I understood all 3 version for it.
Without seeing what you have got in your simulation it is hard to guess what went wrong.
Please note ARM_SOC1 instantiate AHB2MEM_V2.v (see the pdf of the slide in the project directory).
Please make sure you are selecting the right file in your project.
(This load code.hex from software directory.)
regards,
Joseph
I uploaded the Simulation results for ARM_SOC_1. Could you help me outwhere I am doing wrong.
Your reset (RESETn) stay at zero (asserted) and therefore the system cannot start.