Hi,
I trying to build the peripheral around Cortex-M0 IP core thorugh AHB-lite system. Right now I have to integrate Cortex-M0 with the DDR2 SRAM (1Gb) through AHB lite.
I searched on internet which shows interfacing only through core generator (MIG). Is there a way I can use Xilinx core generator to interface through AHB lite system.
I am using Atlys Xilinx Spartan 6.
I also have some example SoC design which interface 128Mb SRAM to Cortex-M0 though AHB lite for Nexsys 3 board . But the Board I am using has DDR2 RAM.
Thanks
If you google
Cortex-M0 DesignStart FPGA
You can find lots of papers and examples from various academic pages.
Here is one of them, a step by step guide:
http://www.latech.edu/tech/liberal-arts/english/html/writing-contest/2012-2013/essays/303_misc-6_Gahagan_ChampyInstructi…
There are also additional papers:
http://www.arm.com/files/pdf/SASE2011_ImplementingTheCortexM0DesignStartProcessorInALowEndFPGA.pdf
Regarding:
a) Generated Bit file - Please refer to Xilinx ISE tutorials
b) Generated bin file from keil - Please check if you should be using bin or hex file first (and which hex file format). This depends on the memory model you use. Then you can add fromelf command in the project option (User tab) to create additional bin/hex files output.
c) Update UCF according to board - Please refer to the examples of the FPGA board your have purchase. Unfortunately we don't have this board so can't help you on this one.
d) I also Stimulated in LSIM and verified. - That's good news. You can then modify the simulated design to toggle an LED on the board and use that as a starting point for hardware testing.
>3) I am using AHB2MEM.v for creating blocking memory for reading and writing. How do I segment it for program and data part?
Please note that this example design does not support byte and halfword write (it support 32-bit write only).
The file AHB2MEM_v1.v seems to support byte and halfword write which would be better. Or you can use the memory model in my paper mentioned in the beginning of the discussion.
In your Keil MDK program image, you can select how much of the memory is reserved for ROM (RO) and how much is reserved for RAM (RW). You can do this in the project settings. For example, if you are going to create a 16KB RAM for both program (8KB) and data (8KB), you can set RO address from 0x0 to 0x1FFF, and RW address from 0x2000 to 0x3FFF.
>4) My friend tried for DDR2 interfacing using MIG and trying to generate a interface for AHB to MIG. Is it a good idea we should try something else
First getting an LED toggling under software control first. If you can't get this step to work you are unlikely to progress further.
regards,
Joseph
1) I have already implemented the above paper for flashing LED under Software control. When Implemented it I saw all LED giving expected output and also glitch which paper mentioned.
2) I was trying for Examlpe ARM _SOC1 and other Mem_control etc. Those example I could not do on board. I run simulation but could not interpret the output.
3) Yeah AHB2MEM I understood all 3 version for it.
Without seeing what you have got in your simulation it is hard to guess what went wrong.
Please note ARM_SOC1 instantiate AHB2MEM_V2.v (see the pdf of the slide in the project directory).
Please make sure you are selecting the right file in your project.
(This load code.hex from software directory.)
I uploaded the Simulation results for ARM_SOC_1. Could you help me outwhere I am doing wrong.
Your reset (RESETn) stay at zero (asserted) and therefore the system cannot start.