I trying to build the peripheral around Cortex-M0 IP core thorugh AHB-lite system. Right now I have to integrate Cortex-M0 with the DDR2 SRAM (1Gb) through AHB lite.
I searched on internet which shows interfacing only through core generator (MIG). Is there a way I can use Xilinx core generator to interface through AHB lite system.
I am using Atlys Xilinx Spartan 6.
I also have some example SoC design which interface 128Mb SRAM to Cortex-M0 though AHB lite for Nexsys 3 board . But the Board I am using has DDR2 RAM.
First of all, why do you want to use the DDR2 memory instead of SRAM inside the FPGA?
You can implement SRAM inside the FPGA for program and data easily.
Also, DDR2 access has latency cycles which means you get lower system performance.
If you definitively need DDR2 then there are plenty of commerical DDR2 memory controllers available.
Just google "DDR2 AHB verilog" returns quite a few products.
If you want free designs I am not aware of anything suiteable. There are some DDR2 memory controller Verilog projects on the web but not AHB based.
(But I didn't try very hard to look for it).
The project I am working on require large storage of data, secondly the board(Atlys board) I am using has 128MB of DDR2 SDRAM. I will check how much memory I can create inside FPGA. I also searched for memory controller but could not find which integrate using AHB Should I go for designing memory controller by myself??
Another thing is that I have to integrate ADC as a peripheral to cortex M0 and my Board does not have any ADC. What can be done for integrating ADC with it?
Can we find ADC IP core for it ? But Analog part of ADC how can that be mapped on FPGA??
You can try modify some of the free DDR2 memory controllers on the web to switch it to use AHB interface. And of course you can create your own DDR2 controller but that would be quite a lot of work.
You cannot design ADC in classic Xilinx FPGA. There are some new products available which support analog components including ADC:
- Xilinx Artix 7, Zynq-7000, Kintex-7 and Virtex-7 (Analog Mixed Signal)
- Cypress PSoC4 (PSoC® 4 - Cypress) and PSoC5LP
- MicroSemi SmartFusion (www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion)
... maybe some more from other vendors
If you have already got you FPGA board, then maybe you can try adding ADC using a parallel or SPI interface.
(If using SPI interface you need a SPI interface module.)
If you haven't brough you board yet, maybe you should consider:
1) ARM Cortex-M Prototyping System (Cortex-M Prototyping System - ARM)
- 8MB of ZBT SSRAM + 16MB PSRAM
- with various system interface IP (Verilog module) for memory
- SPI interface for external SPI ADC
2) SmartFusion Development Kit
- 2MB external SRAM+16MB flash+16MB PSRAM
- System IP included in Libero IDE (please double check with their sales team first. From my understanding the IP is stored in the IDE in protected form so you cannot change or view the source code).
i) I was wondering how much on chip memory I can get on spatran 6 FPGA with cortex M0 running in it.
ii) Making DDR2 controller would be big task.
iii) I was trying for the CMSDK( cortex M system design Kit). Is there module available like AHB to SRAM and for other peripheral? Is there any licencing fee for getting it?
iv) I have zynq 7000 board available in my lab. I checked It has it own cortexA9 processor and XADC as well. But changing board would take time.
i) See Xilinx datasheet
However, please note that even LX45 got 2088Kbits (256Kbytes) of memory, it doesn't necessary means you can fully utilize that in your project.
(e.g. place and routing limitations)
You need to do some homework to test it yourself.
ii) Yes, that's why it is not free.
iii) The full CMSDK product require licensing. But if you buy the Cortex-M Prototyping System (FPGA board), it included a subset of the CMSDK include AHB to external SRAM interface (also work with PSRAM).
iv) They have application note:
Few more thing I need to ask.
1) I have got some example design from ARM website Which I have been trying for 2 days but could not implement on FPGA board.
I tried with Implementing EXample_SoC_1 but how do I check If it is working.
a) Generated Bit file
b) Generated bin file from keil
c) Update UCF according to board
d) I also Stimulated in LSIM and verified.
2) I am facing little difficulty in understanding the Keil code which is there in Example SoC. May be I did some setting wrong in configuring. Clocks and all??
3) I am using AHB2MEM.v for creating blocking memory for reading and writing. How do I segment it for program and data part?
4) My friend tried for DDR2 interfacing using MIG and trying to generate a interface for AHB to MIG. Is it a good idea we should try something else.
If you google
Cortex-M0 DesignStart FPGA
You can find lots of papers and examples from various academic pages.
Here is one of them, a step by step guide:
There are also additional papers:
a) Generated Bit file - Please refer to Xilinx ISE tutorials
b) Generated bin file from keil - Please check if you should be using bin or hex file first (and which hex file format). This depends on the memory model you use. Then you can add fromelf command in the project option (User tab) to create additional bin/hex files output.
c) Update UCF according to board - Please refer to the examples of the FPGA board your have purchase. Unfortunately we don't have this board so can't help you on this one.
d) I also Stimulated in LSIM and verified. - That's good news. You can then modify the simulated design to toggle an LED on the board and use that as a starting point for hardware testing.
>3) I am using AHB2MEM.v for creating blocking memory for reading and writing. How do I segment it for program and data part?
Please note that this example design does not support byte and halfword write (it support 32-bit write only).
The file AHB2MEM_v1.v seems to support byte and halfword write which would be better. Or you can use the memory model in my paper mentioned in the beginning of the discussion.
In your Keil MDK program image, you can select how much of the memory is reserved for ROM (RO) and how much is reserved for RAM (RW). You can do this in the project settings. For example, if you are going to create a 16KB RAM for both program (8KB) and data (8KB), you can set RO address from 0x0 to 0x1FFF, and RW address from 0x2000 to 0x3FFF.
>4) My friend tried for DDR2 interfacing using MIG and trying to generate a interface for AHB to MIG. Is it a good idea we should try something else
First getting an LED toggling under software control first. If you can't get this step to work you are unlikely to progress further.
1) I have already implemented the above paper for flashing LED under Software control. When Implemented it I saw all LED giving expected output and also glitch which paper mentioned.
2) I was trying for Examlpe ARM _SOC1 and other Mem_control etc. Those example I could not do on board. I run simulation but could not interpret the output.
3) Yeah AHB2MEM I understood all 3 version for it.
Without seeing what you have got in your simulation it is hard to guess what went wrong.
Please note ARM_SOC1 instantiate AHB2MEM_V2.v (see the pdf of the slide in the project directory).
Please make sure you are selecting the right file in your project.
(This load code.hex from software directory.)
I uploaded the Simulation results for ARM_SOC_1. Could you help me outwhere I am doing wrong.
Your reset (RESETn) stay at zero (asserted) and therefore the system cannot start.
I still could not figure out what this does and LED is still all ZERO.
In this waveform, the reset get activated every couple of clock cycles. It seem the reset generation in your test bench has some problem.
Sent from my iPad
Actually tried with all reset value Low and High also toggling. But LED signal remain zero all time. If you see here RESETn =1 it is disabled. and for RESETn=0 it gives only the first value of hex file. As the code suggest it should it should toggle b/w 55 and AA?? Please correct me if I am wrong
Please see o/p for both resetn high and low.