Question : The Definitive Guide to the ARM Cortex-M3

Note: This was originally posted on 11th December 2007 at http://forums.arm.com

Dear, all.

I am new in this forum.
Recently I studying Cortex-M3 core, so I bought book "The Definitive Guide to the ARM Cortex-M3" by Joseph Yiu.
This book is very good book and this explains most of unaswered questions by TRM or AALRM.

As I found some mistake in this book, I would like to feedback, but I could not find publisher's homepage. Then I found Josephe's name in this forum, I would like to ask here.

In page 42, there is fig 3.11 and 3.12 but this contents is same as fig 3.8 and 3.9.
Fig 3.8 and 3.9 should be some program list.

Can I get correct figure? Or where I should contact?
Please advise.

Kenichi
  • Note: This was originally posted on 23rd January 2010 at http://forums.arm.com

    Joseph,

    your book is really very useful !!

    There is something though that I can't understand or it is not quite precise. On p.135 you mention a "problem with context switching at IRQ".

    If an interrupt request takes place before the SYSTICK exception, the SYSTICK exception
    will preempt the IRQ handler. In this case, the OS should not carry out the context switching.


    this is correct The OS cannot change the context because the IRQ handler may have changed some of the top registers.

    Otherwise the IRQ handler process will be delayed, and for the Cortex-M3, a usage fault
    could be generated if the OS tries to switch to Thread mode when an interrupt is active.


    I have seen several RTOS implementations and it is also quite logical to use only the PSP for the taks. This means that there is no reason to change the LR when you do a context switch.

    And if you do not touch the LR (in SYSTICK) there will be no usage fault.

    And there is no way to delay the IRQs... The core will first try to tail chain all the IRQs that have higher priority than any stacked, and then the execution will return to the stacked ones if any. No user task can get control before all the IRQs are serviced out.

    So I think that there will be no IRQ delays or usage faults. The real problem is the preemption that can destroy the task contexts and the use of PendSvc is the correct solution. Another solution is to lower enough the SYSTICK priority.
    There is one more thing about the priorities. Sometimes you need to call protected system function (SVCs) not only from user tasks but also from ISRs. This means that the SVC exception must have a mid-priority and all kernel-aware IRQs must have lower priority otherwise they will end up with usage fault if they use the SVC instruction.  Then we will have
    - "fast" IRQs
    - SVC
    - kernel aware IRQs
    - SYSTICK
    - PendSV
    - user tasks

    Miro
  • Note: This was originally posted on 21st January 2010 at http://forums.arm.com

    Thanks Josepth. I was concerned that buying the new edition would be a simple cover change with errata updates. However, it sounds like enough new material to warrent the purchase. So, off to Amazon...  :mellow:

    Dave


    Thanks Dave. Hope you find the book useful. :-)
    Joseph
  • Note: This was originally posted on 21st January 2010 at http://forums.arm.com

    Thanks Josepth. I was concerned that buying the new edition would be a simple cover change with errata updates. However, it sounds like enough new material to warrent the purchase. So, off to Amazon...  :mellow:

    Dave
  • Note: This was originally posted on 20th January 2010 at http://forums.arm.com

    Hi Dave,

    There has been a lot of updates:
    -  the corrections listed on the errata document, as well as various other typo are corrected.
    - GNU tool chain (chapter 19) is completely changed. CodeSourcery tools has changed the C startup handling (CS3). Also, it covers retargetting handling in CodeSourcery tools.
    - CMSIS (Cortex Microcontroller Software Interface Standard) : the new Cortex-M3 device drivers from microcontroller vendors are based on CMSIS.  This allows much better compatibility between various device driver, embedded OS and middleware.
    - More C language examples.  Many examples in the first edition are written in assembly language.  The second edition provides both C language examples and assembly language examples.
    - More information about trouble shooting including common errors, hard fault handler example.
    - Features on Cortex-M3 revision 2 (r2p0), and how does it affect the applications.
    - Differences between Cortex-M3 and Cortex-M0, and software compatibility between them.
    - LabVIEW for ARM.  This is a new chapter about the LabVIEW embedded module for ARM.
    - Detailed instruction set from the ARM Cortex-M3 User Guide (replacing the previous instruction set table in appendix A)
    - Improved descriptions/illustrations on various topics. E.g. chapter 3 instruction set has overlapping information removed and some additional information added
    - New appendixes : CMSIS functions, CodeSourcery linker script, Debug connector arrangement

    The "TI" version is not prepare by me.  I guess TI/Luminary might has licensed the copyright of the materials from the book publisher and modifying it to cover more information on their products.  But I don't have any details on that. Sorry.

    regards,
    Joseph
  • Note: This was originally posted on 20th January 2010 at http://forums.arm.com

    Josepth,

    Hello. I was wondering if you can tell me what the difference between the new Elsivier (Newness) edition of you book and the 2007 edition? I own the 2007 edition and was considering the newer edition depending on the changes. I assume corrections (per may of the errata individuals have submitted here of course) but in term of new content? I found your book to be indispensible with respect to learning the Cortex M3. I also noticed you have a new book coming out shortly with CD ROM that, more or less, implies "TI". I would assume there will be material covering the Luminary series? Can you shed some light on that book?

    Thanks,

    Dave Comer
  • Note: This was originally posted on 25th September 2009 at http://forums.arm.com

    Yes, you're right. Another copy-and-paste error... ouch.
    Joseph
  • Note: This was originally posted on 25th September 2009 at http://forums.arm.com

    Hi Joseph,

    I didn't notice these ones !

    But on page 80, I think that the line :
    STRD.W R0, R1, [R2, #0x20] ; This will gives memory[0x1000] = R0,
                               ; memory[0x1004] = R1

    should be :
    STRD.W R0, R1, [R2, #0x20] ; This will gives memory[0x1020] = R0,
                               ; memory[0x1024] = R1

    Jean-Claude
  • Note: This was originally posted on 24th September 2009 at http://forums.arm.com

    Hi Jean-Claude,
    Thanks for let me know.  Sorry for these errors. (working on this late at night is not good  :D ).
    There is another two:
    1) Table 4.29:

    Input (R0)          Output (R1)     Q Bit
    0xFFFF8001   0xFFFF8000  Set

    This row should have been
    0xFFFF7FFF   0xFFFF8000  Set

    2) Table 4.30
    0x00008000   0x00008000   Set

    This row should have been
    0x00008000   0x00008000   Unchanged

    Please continue to inform me if you find any other errors, and
    feel free to contact me directly if you want more information.
    Thanks
    Joseph
  • Note: This was originally posted on 24th September 2009 at http://forums.arm.com

    Another one, on page 74 :

    "Similarly, if a 32-bit signed value ..."
    should be :
    "Similarly, if a 32-bit unsigned value ..."


    The IF-THEN instructions are described twice, on page 71 and 76.

    The CBZ-CBNZ instructions are described twice, on page 70 and 77.
  • Note: This was originally posted on 24th September 2009 at http://forums.arm.com

    Another error, on page 65 :
    In table 4.22, a register is named Rm in the instructions, but Rn in the comments.
  • Note: This was originally posted on 24th September 2009 at http://forums.arm.com

    Hello Joseph,

    I have found another error, on page 53:
    REV Byte reserve word, instead of Byte reverse word

    Jean-Claude
  • Note: This was originally posted on 14th August 2008 at http://forums.arm.com

    Hi all,

    The errata document for the book is updated (see attached file).

    Joseph
  • Note: This was originally posted on 14th April 2008 at http://forums.arm.com

    Hi Kenichi,

    The errata document for the book is updated (see attached file).

    Joseph
  • Note: This was originally posted on 16th January 2008 at http://forums.arm.com

    Hi Kenichi,

    The table is correct. The WFI behaviour is different from WFE on this point.
    If you look at ARM v7-M Architecture Application Level Reference Manual (ARM DDI-0405), in the WFI instruction description, there is a note specifying this behaviour.

    regards,
    Joseph
  • Note: This was originally posted on 16th January 2008 at http://forums.arm.com

    Dear, Joseph.

    I have another question regarding "The Definitive Guise to the ARM Cortex-M3"

    Page 228, Table 14.2  WFI and WFE Wake Up Behavior
    For the WFE Behavior part,
    IRQ with BASEPRI and PRIMASK, SEVONPEND=0
    IRQ priority > BASEPRI
    Wake Up is N.
    But WFI Behavior it wakes up (in this case SEVONPNED is don't care)

    Can you verify this condition does not wake up?

    If my explanation is not clear please let me know.

    Regards.
    Kenichi
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