Arm Community
Site
Search
User
Site
Search
User
Groups
Arm Research
DesignStart
Education Hub
Graphics and Gaming
High Performance Computing
Innovation
Multimedia
Open Source Software and Platforms
Physical
Processors
Security
System
Software Tools
TrustZone for Armv8-M
中文社区
Blog
Announcements
Artificial Intelligence
Automotive
Healthcare
HPC
Infrastructure
Innovation
Internet of Things
Machine Learning
Mobile
Smart Homes
Wearables
Forums
All developer forums
IP Product forums
Tool & Software forums
Support
Open a support case
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
Community Help
More
Cancel
Developer Community
IP Products
Processors
Jump...
Cancel
Processors
Cortex-M / M-Profile forum
Question : The Definitive Guide to the ARM Cortex-M3
Blogs
Forums
Videos & Files
Help
Jump...
Cancel
New
State
Not Answered
Replies
33 replies
Subscribers
6 subscribers
Views
15050 views
Users
0 members are here
Cortex-M3
Cortex-M
Related
Question : The Definitive Guide to the ARM Cortex-M3
Offline
Kenichi Kenichi
over 7 years ago
Note: This was originally posted on 11th December 2007 at
http://forums.arm.com
Dear, all.
I am new in this forum.
Recently I studying Cortex-M3 core, so I bought book "The Definitive Guide to the ARM Cortex-M3" by Joseph Yiu.
This book is very good book and this explains most of unaswered questions by TRM or AALRM.
As I found some mistake in this book, I would like to feedback, but I could not find publisher's homepage. Then I found Josephe's name in this forum, I would like to ask here.
In page 42, there is fig 3.11 and 3.12 but this contents is same as fig 3.8 and 3.9.
Fig 3.8 and 3.9 should be some program list.
Can I get correct figure? Or where I should contact?
Please advise.
Kenichi
Parents
0
Offline
guestposter guestposter
over 7 years ago
Note: This was originally posted on 23rd January 2010 at
http://forums.arm.com
Hi Miro,
Good questions!
In the case of having an IRQ running, and if the IRQ is lower priority than SysTick, then proceeding on context switching usually means the PSP is changed to point to the stack frame of a a different task.
As a result, when you execute exception return, the PC value of another task will be used and you will end up executing the other tasks with privilege level of the IRQ, which can be bad (user task running at privileged level, and all other IRQs at the same or lower priority level will be blocked). Therefore context switching code could modify LR to ensure it is switching to unprivileged level, but then it lead to usage fault due to trying to run in Thread mode with an active IRQ.
In practice I believe Cortex-M3 will flag a usage fault even if LR is not modified because it has various system integrity checkings. When switching to the other task with IPSR equal 0 (which is unstacked from the other task's stack frame) and having an active IRQ should trigger a fault (need double check).
Lower the SysTick priority is one solution, but if an IRQ handler is not function properly (e.g. accidental software deadloop) the SysTick will not be able to preempt and the system will be frozen.
Yes, it if possible to have a mid-priority level SVC so that an OS aware IRQ handler can use the SVC function. But instead of using SVC, you might able to call the SVC function directly rather than using SVC exception. This is better if you need to port the software to Cortex-M0, which has 4 levels of priority levels.
Hope this answered your questions and feel free to let me know if you need further explanations.
regards,
Joseph
Cancel
Up
0
Down
Reply
Accept answer
Cancel
Reply
0
Offline
guestposter guestposter
over 7 years ago
Note: This was originally posted on 23rd January 2010 at
http://forums.arm.com
Hi Miro,
Good questions!
In the case of having an IRQ running, and if the IRQ is lower priority than SysTick, then proceeding on context switching usually means the PSP is changed to point to the stack frame of a a different task.
As a result, when you execute exception return, the PC value of another task will be used and you will end up executing the other tasks with privilege level of the IRQ, which can be bad (user task running at privileged level, and all other IRQs at the same or lower priority level will be blocked). Therefore context switching code could modify LR to ensure it is switching to unprivileged level, but then it lead to usage fault due to trying to run in Thread mode with an active IRQ.
In practice I believe Cortex-M3 will flag a usage fault even if LR is not modified because it has various system integrity checkings. When switching to the other task with IPSR equal 0 (which is unstacked from the other task's stack frame) and having an active IRQ should trigger a fault (need double check).
Lower the SysTick priority is one solution, but if an IRQ handler is not function properly (e.g. accidental software deadloop) the SysTick will not be able to preempt and the system will be frozen.
Yes, it if possible to have a mid-priority level SVC so that an OS aware IRQ handler can use the SVC function. But instead of using SVC, you might able to call the SVC function directly rather than using SVC exception. This is better if you need to port the software to Cortex-M0, which has 4 levels of priority levels.
Hope this answered your questions and feel free to let me know if you need further explanations.
regards,
Joseph
Cancel
Up
0
Down
Reply
Accept answer
Cancel
Children
No data
More questions in this forum
By title
By date
By reply count
By view count
By most asked
By votes
By quality
Descending
Ascending
All recent questions
Unread questions
Questions you've participated in
Questions you've asked
Unanswered questions
Answered questions
Questions with suggested answers
Questions with no replies
Not Answered
Compiling libgcc not optimized
0
32-bit
Armv7-M
Compiling
GCC
Thumb
Cortex-M
Thumb2
Library
Arm Assembly Language (ASM)
C
Cortex-M4
2255
views
11
replies
Latest
3 months ago
by
a.surati
Not Answered
How to specify RAM location ?
0
SRAM
STM32 F1
Arm Assembly Language (ASM)
641
views
1
reply
Latest
3 months ago
by
GuillaumeP
Answered
Is it possible to enable or disable the nested interrupt mechanism on M0 ?
0
672
views
2
replies
Latest
3 months ago
by
Robert McNamara
Answered
How long are the Cortex-M7 pipeline stages?
0
Cortex-M7
Cortex-M
30834
views
18
replies
Latest
3 months ago
by
Pacocha
Not Answered
How to transfer and read weights, biases and activation functions from trained tensorflow model to nucleo-f446re or any microcontroller in keil
0
Embedded
Neural Network
Keil
TensorFlow
CMSIS
399
views
0
replies
Started
3 months ago
by
PrashanthPoobalan
<
>
View all questions in Cortex-M / M-Profile forum