Cortex-M: Does the event register only get set when an IRQ changes from not pending to pending?

I recently had a race-condition in an application on a Cortex-M4 microcontroller, because I used a wrong order of __SEV() and __WFE() instructions to put my chip to sleep. While debugging this issue, I wondered when exactly the event register does get set. (Link to my related question in the Nordicsemi Developer zone)

Let's assume the following scenario:

  • the SEVONPEND-Bit is set in the SCR.
  • I have cleared and enabled interrupts on PERIPHERAL_IRQn via NVIC.
  • For some reason, the associated peripheral fires an interrupt and PERIPHERAL_IRQn is set to pending, but the interrupt does not get served. E.g. PRIMASK is set to a value masking this particular interrupt's priority.

Does the event register get set in that case? I assume yes, because according to the reference manual:

In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority
to cause exception entry.

Suppose I clear the event flag by calling _WFE(), and after that the same peripheral fires another interrupt while PERIPHERAL_IRQn is still pending. Does the event register get set again? I assume no, because the manual specifies "any new pending interrupt triggers an event". Because that IRQn was already pending and did not change its state, the event register would not get set again.

Am I right with this assumption?

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