I am currently working on a cortex-M0 microprocessor(LPC1114). I have looked through all the possible instruction descriptions but I did not find anyone of them explaining why some instructions takes two cycle to execute.
For example, ANDS, MOVS takes only one cycle to execute. but why do we need two cycles to execute LDR? and STR?
Because those need the external bus. All other instructions use just registers (== internal "bus").
Thanks so much for your answer.
So there will be a pipeline stall for LDR and STR to allow the bus to fetch the data?
For example, assume I have a LDR PC-relative instruction as LDR R4, =(#0xFEDCBA98);
Assume at cycle 0, this instruction is fetched with another instruction (assume it as NOP),
At cycle 1, the LDR pc-relative instruction is decoded
at cycle 2, the ldr pc-relative instruction is executed and also the final address of the data is calculated as PC+ offset here
at cycle 3, the processor has a pipeline stall stage to let the bus write back the value to R4 register.
The above picture is a timing diagram,
Assume FEDCBA98 is stored at address 0x074. cycle 2 is the execution cycle of LDR R4 =(0xFEDCBA98) instruction. Thus, PC+offset is ready at time t2 (some delay after clock edge 1). Then, data will be available on the bus at time t2, and write back to the register at clock edge 3.
Cycle 3 is the pipeline stall stage.
Please correct me if I am wrong.
Thanks so much!
Sorry, I have no idea about pipeline etc.
Cortex-M0 is based on a simple 3 stage pipeline design: Fetch, decode, execute.
The data access starts at execution stage - due to pipeline nature of AHB bus protocol, the data transfer is 1 cycle after the execution stage. As a result, the pipeline is stalled for 1 cycle. Hence for single load and store instructions, it takes 2 cycles on Cortex-M0.
In Cortex-M3, although it is also based on AHB bus protocol, the store operation can hide the stall cycle using a write buffer (i.e. instruction is treated as completed even the bus transaction on bus interface is not completed).
Thanks so much for the explanation!