Understanding XDMAC on Cortex-M7

I've inherited some XDMAC code and no one that wrote this code really seems to be able to explain anomalies that I am seeing. So, I'm trying to understand just the basics in an attempt to make sure it was written correctly in the first place. Here we have an audio CODEC attached over I2S to the M7 and we're doing DMA to a ping pong buffer for audio processing. While we have only two buffers in the resulting linked list I imagine my question should apply to an arbitrary number.

Specifically, in the ISR the code is reading the CNDA register in order to figure out which buffer needs to be sent for processing. Here we have some misunderstanding of what this register means when we read it in the ISR.

Since the ISR fires when DMA is complete for, say, "buffer 3" is CNDA going to be pointing to "buffer 4" (as in, "we have finished with buffer 3 and buffer 4 is about to be written to") or will it be pointing to "buffer 5" (as in, "we have finished with buffer 3, we are currently writing to buffer 4, and we will start on buffer 5 next")?

I have to imagine this is a pretty basic question but it will help me understand if this code is written correctly in the first place.

Thanks!

- Paul Braman

  • First, this is the ARM Community, for questions related to ARM processors.

    Second, CNDA register is a Channel Next Descriptor Address Register of XDMAC controller (Atmel - Microchip).

    Find out to which SMART ARM-based Flash MCU families your controller belongs.

    Then go to the Microchip website and download datasheet.

    From datasheet you can understand the purpose of CNDA register as a part of XDMAC controller, furthermore datasheet provides functional description of XDMAC.

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