NVIC and ARM asm

Cannot configure interupts of TIM6 on stm32f103 board

Does my NVIC configuration wrong?


@ stm32f103 timer & interrupt test by laper_s (from 2019-02-02)

.cpu cortex-m3
.syntax unified

.word   0x20005000
.word   start + 1

b   start

.macro mov32 regnum,number
    movw \regnum,:lower16:\number
    movt \regnum,:upper16:\number

    mov32 r1, 0x40021018  @ RCC_APB2ENR address
    mov32 r0, 0x10        @ enable GPIOC
    str   r0, [r1]

    mov32 r1, 0x4002101c  @ RCC_APB1ENR address
    mov32 r0, 0x10        @ enable TIM6
    str   r0, [r1]

    mov32 r1, 0x40011004  @ GPIOC_CRH
    mov32 r0, 0x44344444  @ set PC13 as 50 MHz PP output
    str   r0, [r1]

    mov32 r1, 0xE000E104  @ NVIC_ISER1
    ldr   r0, [r1]
    orr   r0, #0x00400000 @ enable interrupt #54
    str   r0, [r1]

    mov32 r1, 0x00000118  @ TIM6 interrupt address
    adr   r0, tim6_interrupt_observer
    str   r0, [r1]
    mov32 r1, 0x40001024  @ TIM6_CNT
    movw  r0, 0x707       @ set counter
    strh  r0, [r1]

    mov32 r1, 0x40001028  @ TIM6_PSC
    movw  r0, 0x270f      @ set prescaler
    strh  r0, [r1]

    mov32 r1, 0x4000100c  @ TIM6_DIER
    movw  r0, 0x1         @ enable update interrupt
    strh  r0, [r1]

    mov32 r1, 0x40001000  @ TIM6_CR1
    ldrh  r0, [r1]
    orr   r0, 0x1         @ enable counter
    strh  r0, [r1]

.include "sysclk.inc"
    b     loop

    mov32 r1, 0x40001010  @ TIM6_SR
    movw  r0, 0x0         @ clear interrupt flag
    str   r0, [r1]

    mov32   r1, 0x4001100c  @ GPIOC_ODR
    ldr     r0, [r1]
    and     r0, #0x2000
    cmp     r0, #0x2000

    ite     eq

    movweq  r0, 0x0000
    movwne  r0, 0x2000
    str     r0, [r1]

    bx      lr
    b     end

Can anyone help me with that?

Parents Reply Children
More questions in this forum