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Cortex-M unintentional Flash Read-While-Write
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Cortex-M7
Memory Protection Unit (MPU)
Cortex-M
Related
Cortex-M unintentional Flash Read-While-Write
Offline
piotr_r
over 2 years ago
Hello,
I am developing a bootloader for the ARM Cortex M7. All the functions that modify (either write or erase) the internal Flash are run from the RAM memory, the other code is run from the internal Flash. So there are RAM <-> Flash transitions in the bootloader execution flow.
It works just fine. But there is one thing that I would like to consult with the experts.
I'd like to ask if either cache or the processor's processing pipeline, with e.g. speculative fetches and branch prediction, can be a safety concern in that case.
I'd like to know answers to the following questions:
1) If the code is being executed from RAM, but the MCU decides to fetch code from the internal Flash, when the Flash is being written at the same time. Is it Flash access that may cause the processor to stall or do something unexpected?
2) If yes, then how to prevent it?
I will appreciate your help.
Thanks,
Piotr
Top replies
Offline
Joseph Yiu
over 2 years ago
in reply to
42Bastian Schick
+2
verified
Things could get a bit messy with branch prediction. It is possible for the cortex-M7 to speculatively prefetch instructions in other "Normal" memory locations due to misprediction. Normally, you won...
Offline
42Bastian Schick
over 2 years ago
+1
verified
How _your_ MCU reacts on Flash read while writing can only be answered by the manufacturer (ideal: it can be found in the manual). Common traps are enabled interrupts and the vector table still points...
Offline
42Bastian Schick
over 2 years ago
in reply to
piotr_r
+1
I doubt that there will be someone with an guarantee. But from my understanding, turning off caches and executing from RAM will prevent further read access. Maybe some data barriers are needed in case...
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