DMB, DSB, ISB on Cortex M3,M4,M7 Single Core parts

I have been reading through the ARM documentation on memory and instruction barriers. 

I have read that the single core ARMv7-M parts do not reorder instructions, as such the DSB and ISB are not needed, is this correct? 

I have also read the same about DMB, however their is a concern across clock domains. For example if peripheral is running at lower clock speed then writing to the  peripheral could take a long time.  For example imagine that you clear and interrupt flag in peripheral during ISR, then if the clear does not happen before exiting the ISR it could trigger falsely trigger ISR again.   Hence I was wondering if DMB would fix the problem across clock domains like this?  Then if so does this only happen with core data cache enabled? 

That is how can the core change the volatile flag register but write takes longer unless the peripheral has a local cache, in which case how does the core know the peripheral local cache register has been applied? 

So in what cases when you have a single core part would DSB be appropriate in code?  Then the same for DSB an ISB? 

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