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Users of Arm processors can be all over the planet, and now they have a place to come together. The processors community is the place to be all things processor-related.
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translation table APTable permission problem
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9 hours ago
Regarding Visibility of Multi Master ACE-Lite System
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the linux kernel will be hung here as long as there are more than one core inside one cluster
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2 months ago
A72 Invalidate dirty cache line (DC IVAC)
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17 days ago
TrustZone- Confidential Computing- TEE
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ARM Neon vs Intel SSE
0
6722
views
1
reply
Latest
2 months ago
by
42Bastian Schick
Answered
How Can I jump from EL1 to EL0 in bare metal environment
0
EL1
ARMv8 Exception Model
EL0
Armv8-A
Arm64
7897
views
3
replies
Latest
2 months ago
by
42Bastian Schick
Not Answered
Arm64 Long Format Translation Table Walk
0
Armv8-A
Memory Management Unit (MMU)
6340
views
0
replies
Started
2 months ago
by
angeld
Suggested Answer
How long does it take for Cortex A53 to exit low power state?
0
6411
views
2
replies
Latest
2 months ago
by
Andy Neil
Not Answered
Optimization of Neon Intrinsics on ARM cortexa53
0
Cortex-A53
AArch64
Optimization Solution
GCC
NEON
Arm Assembly Language (ASM)
7818
views
12
replies
Latest
2 months ago
by
42Bastian Schick
Not Answered
How To Swap From 32-bit Mode To 64-bit Mode In An Android that has ARMV8-A OS
0
6651
views
1
reply
Latest
2 months ago
by
42Bastian Schick
Not Answered
Problem in understanding behaviour of GCC compiler (aarch64-none-elf-gcc) on Neon intrinsics for ARM cortex a53
0
Cortex-A53
Optimization Solution
GNU Assembler
GCC
NEON
Compilers
9968
views
10
replies
Latest
2 months ago
by
khan777
Not Answered
Debugging using DS5 and Foundation model: Interrupt is not forwarded to the CPU.
0
AArch64
GICv2
DS-5 Ultimate Edition
Armv8 Foundation Platform
DS-5 Technical Support
8124
views
4
replies
Latest
3 months ago
by
Jorge
Not Answered
arm CC compiler on ARM cortex a53
0
8437
views
3
replies
Latest
3 months ago
by
khan777
Not Answered
ACE VIP
0
6745
views
0
replies
Started
3 months ago
by
Enthusiastic learner
Not Answered
Cortex A-35 cluster interference
0
6739
views
0
replies
Started
3 months ago
by
David
Not Answered
Unusual time in booting secondary cores on ARMV8 platform (Zynq MPSoc)
0
Power state coordination Interface
Armv8-A
TrustZone
7219
views
2
replies
Latest
3 months ago
by
Saud
Not Answered
A low-overhead real time counter consistent cross processor cores
0
7406
views
0
replies
Started
3 months ago
by
BeniFalk
Answered
LEARNING | Development Boards
0
Analog & Asynchronous Design
Development Boards
Internet of Things (IoT)
10721
views
4
replies
Latest
3 months ago
by
Andy Neil
Not Answered
How can I configure BTAC and GHB size?
0
7886
views
0
replies
Started
3 months ago
by
w38245
Not Answered
Why do we have to send HMASTLOCK signal to the slave?
0
AHB-Lite
Cortex-A
AHB
15326
views
1
reply
Latest
3 months ago
by
Xingguang Feng
Not Answered
To the Website admin : problem download a resticted non-confidential document
0
9422
views
1
reply
Latest
3 months ago
by
LATH
Not Answered
DVFS implementation in C
0
9103
views
2
replies
Latest
3 months ago
by
Mohammed Bey
Suggested Answer
EDSCR err bit set after a write to EDITR
0
Cortex-A57
AArch64
Armv8-A
10495
views
6
replies
Latest
3 months ago
by
kka
Not Answered
Autodetect SDRAM size in uBoot Bootloader via ARMv7 processor exception handler
0
Armv7-A
Armv7 Exception Model
9454
views
3
replies
Latest
3 months ago
by
42Bastian Schick
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