• -print-libgcc-file-name gives thumb while -marm is used

    Dear Forum,

    Using

    ~$ arm-none-eabi-gcc -v                                                                             
Using built-in specs.
COLLECT_GCC=arm-none-eabi-gcc
COLLECT_LTO_WRAPPER=/opt/gcc-arm-none-eabi/bin/../libexec/gcc/arm-none-eabi/9…

  • Cortex A code / function alignment

    Hi !

    I am writing assembly code for some ARMv7a and ARMv8a CPU. I know that code has to be 4 bytes aligned, but I saw in several places (uboot/linux) the ".align 4" GCC directive, which will align to 2**4 = 16 bytes.

    When writing code that will…

  • UPREDICTABLE instructions

    Any idea about instructions marked as UNPREDICTABLE: can it then be UNDEFINED?

    In other words: UNDEFINED REQUIRES the instruction to cause UND-exception, but

    MAY UNPREDICTABLE do that, or does it have to execute normally except that the result may be…

  • The madman strikes again - ADD/SUB SP

    Is there something special in the instructions ADD (SP plus register, ARM) and SUB (SP minus register)?

    I didn't find anything different from the basic ADD  (register) and SUB (register) except the documentation:

    <Rd> The destination register…

  • What does it mean 'IT can be omitted'?

    Hi,

    When I read the following on ARM website, I don't understand the first line. When I change ITTE to TE (as 'IT can be omitted"), the assembler complains an error of this line.

    Could you explain it to me?

    Thanks,

      ITTE NE ; IT can be omit…

  • Question about a code snippet on ARM, Thumb state change

    Hi,

    I find the following code snippet online on ARM state change. Although that whole material looks solid, the second line in the blue code below is puzzling.

    add R1,PC,#1 ;Load address of SUB_BRANCH, Set for THUMB by adding 1

    I don't see how the above…

  • IT CPZ CPNZ

    My Thumb 16-bit Instruction Set 'Quick Reference Guide' is permanently displayed on one of my monitors. I note several instructions that are at once listed but are marked as T2 i.e.

    (If then)                                   IT {pattern} {cond}
    (compare/branch) 

    …

  • ELF entry point in thumb mode (armv7/aarch32)

    Hi !

    We are writing an OS targeting 32 bits ARM platform, where binaries can be compiled in ARM or in Thumb mode.

    At the moment, to execute a new process, I load the info from an ELF, set lr_usr to the entry point address, set spsr_usr to a default value…

  • How many states for an ARM Cortex A8?

    Hi,

    When I read about Thumb2 instructions, I have such a question: How many states for a Coretx A8? I know it has ARM and Thumb states. Thumb2 instruction is belong to Thumb state? Then does A8 have a pure Thumb instruction besides Thumb2 set?

    Thanks,

  • Why the different encodings?

    Why are there different encodings of instructions?

    What's the idea/background/etc for their co-existence?

    Can different encodings be mixed in the code? (Not ARM encodings with Thumb encodings- without ARM/Thumb mode change,

    but, like A1 and A2 or T1…

  • Difference between thumb machine directives

    Hi Experts,

    What is the key difference between the following directives

    .thumb

    .thumb_func

    .force_thumb

    .thumb_set

    What is the exact use case where the above things can to be applied ?

    Regards,

    Techguyz

  • Is Thumb to ARM mode overhead

    Hi all,

    Consider high priority routines are executing in ARM mode and low priority in Thumb mode. There could be constant switching between ARM and THUMB mode. In this inter-working model is there any overhead due to the mode switching ?