Hi,

i'm currently trying to measure cycle counts for FIR-filtering with the NE10 library. I'm using a Raspberry Pi 2 with ARM Cortex-A7 running on Raspbian as a target.

I activated the Cortex-A7 performance counter register to read out the cycles…

I'm seeing Cortex-A7 cycle-timing table here :

http://hardwarebug.org/2014/05/15/cortex-a7-instruction-cycle-timings/

For example, 

VADD.F32 Dd, Dn, Dm takes 2 cycles

VADD.F32 Qd, Qn, Qm takes 4 cycles

same goes for VMUL..

Is this really the case…

The cortex-A7's pipeline support dual-issue, so I want to ask what's the dual-issue mean?

I find some answers say that dual-issue means that the cortex-A7 can issue two instructions per clock.

But in the cortex-A7's pipeline diagraph, it has integer…