• Issues in Cortex A9 bareboard code if L2 cache controller registers are not mapped

    Hi

    I have written a bareboard code for i.MX6 (Cortex A9 Quad core). I am activating and using only one core.  Once I enable the MMU, code throws random exceptions. Both L1 and L2 caches are disabled. The interesting part is that if I just map the memory…