• Getting processor and cache details

    I work on software that needs to know the processor and cache details. On x86 systems it uses the CPUID instruction to know about the processor family/model (Skylake, Icelake etc) and cache details (total size, line size, associativity etc). I am trying…

  • Flushing all L1 & L2 caches under Linux (kernel space) - optimizing dma-mapping API

    Hi,

    In my system (CycloneV - 2 cores of Cortex-A9) I require large DMA transfers, and currently I can't connect DMA via ACP, so cache coherency becomes SW problem. I know that the proper way of doing it under Linux is using the DMA-MAPPING API, and…

  • ARMv7 "write buffer" issue

    Note: This was originally posted on 3rd July 2012 at http://forums.arm.com

    Hi All,

    I have a question about the "write buffer" for ARMv7 processor.

    Write buffer is explicitly described in TRM(tech reference manual) prior to ARMv6. E.g, how to enable…

  • [ARMv7] question about writel & barrier

    Hi Sirs,

    I got a question about the way Linux 3.18 defines the "writel()".

    In linux-3.18/arch/arm64/include/asm/io.h, it describes:

    /*

    * I/O memory access primitives. Reads are ordered relative to any

    * following Normal memory access. Writes are…

  • Unhandled fault: alignment fault (0x92000061) at 0x00000000fff0f729

    Hi,

    I have an arm cortex A-57 machine that is running 3.16 linux kernel (64bit) compiled using gcc-linaro-aarch64_be-linux-gnu-4.9-2014.09_linux toolchain.

    My application (32bit) is accessing a member inside a structure at unaligned address using pointer…

  • Share aarch64 page tables created by Linux with SMMU

    Hello!

    I am currently working on creating a shared virtual address space in Linux arm64 on a Xilinx Zynq Ultrascale+ board. In the future it should be possible to share pointers/addresses between the Cortex A53s and the FPGA utilizing the built in ARM…

  • How do I probe in for Power measurement in A9 using PAPI tool

    Hi,

    I am new to the forum and also to the community. I am trying my best to reach out for help yet meeting the standards of the community. I have been working on ARM Cortex A9 MPcore processors that are on-board the Zedboard ( which is a Zynq Evaluation…

  • Raspberry Pi 2 JTAG error on memory access

    Hi all,

    I am trying to connect to the RPi2 JTAG.

    I have the following setup

    - Raspberry Pi 2 running Raspbian 8.0 (Jessie)

    - OpenOCD 0.9.0 with a J-Link EDU connected to a Ubuntu system.

    I setup the GPIO in order to expose the JTAG interface and the…

  • ARM Cortex A9 flush cache

    I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements.

    Is it doable from user mode?

    Processor: ARM Cortex A9

    OS: Linaro Linux

  • How can we boot linux kernel in ARM FVP w/ TrustZone?

    Hello, everyone.

    Let me post a question regarding booting Linux on ARM FVP (with Cortex-A9 MPCore).

    I'm setting up an experiment which uses TrustZone on ARM FVP. I'm not sure which

    kernel to run in the secure world, but am sure to run Linux in Normal…

  • Accurate cycles measurement

    Dear experts,

    I am currently trying to measure the cycles required to context switch between two linux processes and the cycles required to world-switch between two linux VMs running above a thin bare-metal hypervisor. For this purpose, I am using the…

  • ARMv8 backwards compatibility with ARMv7

    Hi there,

    I have been going through a lot of ARMv8 documents, and I have a very basic question:

    -Can I take a Linux Kernel, compiled for a ARMv7 device, and run it on an ARMv8 device in Aarch32 execution mode?

    ( Lets assume that the two SOCs are identical…

  • Help me jump into ARM world !(I know nothing but AVR)

    Hi,  Sorry if this is a long thread but i'm really confused.

    I program for AVR MCUs and also know about Arduino, I can program for different ATMEL MCUs with looking at datasheets, And i also programmed a few basic stuff on Cortex-M3 LPC1768, without…

  • Cortex-A9 secondary boot Procedure

    I am trying to enable SMP  functionality  for our custom target having a dual core.

    Below is my understanding w.r.t Basic ARM secondary CPU boot address:

    a. The secondary CPU is provided with some registers (named like BOOTUP REG) to keep the…