• Multicore SMP using Linux kernel

    Hi,

    I am just trying to learn the linux kernel booting process for arm32 Cortex A9 multi core SOC. I had understood the concept of booting in linux, but I am confused about the section where secondary cores enabling from primary core. Can somebody briefly…

  • How to use DMA for Cortex-A9 ?

      hello, I want to use DMA 330 asm code, but i can't compile it. can anyone tell how to use the PLL330 DMA assembly code? or tell me how to use the DMA for Cortex-A9

  • SMP ARM cores hang when using DMA and two cores enabled

    Hi,

    I am experiencing A complete arm core hang when both of the cores are employed in SMP mode and using DMA.

    I was tested with Linux kernels 3.10, 4.1 and 4.6 in SMP mode.

    SOC used is Altera Cyclone V SOC-FPGA with dual Cortex A9.

    The DMA transfer goes from…

  • share memory between core0 (linux) and core1 (bare-metal)

    Hello,

    i want to use the arm cortex a9 to share memory between both cores. are there any examples online?

    Thanks,

    Mike

  • How to run an ARM 32bit binary on Juno Board in Linux and Android ?

    hi, guys:

    Currently, i want to execute a Cotex-A9 binary compiled by ARMCC on Juno board(OS is linux).

    But when i ran it, it reported that "XX: No such file or directory".

    My questions are:

    (1) Did somebody meet this problem before ?

          and could…

  • Software Radio Based on ZedBoard and AD-FMCOMMS1-EBZ

    ARM friends,

    I have done some research on software radio based on ZedBoard and AD-FMCOMMS1-EBZ.

    ZedBoard is a development board which uses Xilinx Soc FPGA.

    Xilinx Soc FPGA includes ARM Cortex A9 dual-core and Xilinx FPGA.

    ZedBoard runs Ubuntu Linux operating…

  • How should I do if I want to enable only one single CPU on a Cortex A9 MPCore(2 CPUs)

    Hi, all

    When I was porting Minix 3 OS to Zedboard (Zynq 7000 All Programmable SoC) the system always hanged

    at refresh_tlb. What's strange is that refresh_tlb had been performed at KERNEL booting up, but when a user

    space process VM (for Virtual Memory…

  • How can we boot linux kernel in ARM FVP w/ TrustZone?

    Hello, everyone.

    Let me post a question regarding booting Linux on ARM FVP (with Cortex-A9 MPCore).

    I'm setting up an experiment which uses TrustZone on ARM FVP. I'm not sure which

    kernel to run in the secure world, but am sure to run Linux in Normal…

  • ARM Cortex A9 boot from spi-flash 32M

    Hi, we are using arm cortex-a9 booting from spansion s25fl256. We are confused why the spi driver forces to limits flash size to 0x1000000 (16M). It's normal when first bring up and into linux. However, we find the uboot is broken or overrided and can…

  • Flushing all L1 & L2 caches under Linux (kernel space) - optimizing dma-mapping API

    Hi,

    In my system (CycloneV - 2 cores of Cortex-A9) I require large DMA transfers, and currently I can't connect DMA via ACP, so cache coherency becomes SW problem. I know that the proper way of doing it under Linux is using the DMA-MAPPING API, and…

  • How do I probe in for Power measurement in A9 using PAPI tool

    Hi,

    I am new to the forum and also to the community. I am trying my best to reach out for help yet meeting the standards of the community. I have been working on ARM Cortex A9 MPcore processors that are on-board the Zedboard ( which is a Zynq Evaluation…

  • ARM Cortex A9 flush cache

    I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements.

    Is it doable from user mode?

    Processor: ARM Cortex A9

    OS: Linaro Linux

  • Cortex-A9 secondary boot Procedure

    I am trying to enable SMP  functionality  for our custom target having a dual core.

    Below is my understanding w.r.t Basic ARM secondary CPU boot address:

    a. The secondary CPU is provided with some registers (named like BOOTUP REG) to keep the…