• ARM v8 PMU Cycle counter

    All,

    When I am using the cycle counter in AArch64, I am not getting cycles properly. I have enabled read of pmccntr_el0 in user space using a small kernel module. I have sample code like:

    asm volatile("isb;mrs %0, pmccntr_el0" : "=r"(prev));

    sleep…

  • ARMv7 "write buffer" issue

    Note: This was originally posted on 3rd July 2012 at http://forums.arm.com

    Hi All,

    I have a question about the "write buffer" for ARMv7 processor.

    Write buffer is explicitly described in TRM(tech reference manual) prior to ARMv6. E.g, how to enable…

  • [ARMv7] question about writel & barrier

    Hi Sirs,

    I got a question about the way Linux 3.18 defines the "writel()".

    In linux-3.18/arch/arm64/include/asm/io.h, it describes:

    /*

    * I/O memory access primitives. Reads are ordered relative to any

    * following Normal memory access. Writes are…

  • ARMv8 backwards compatibility with ARMv7

    Hi there,

    I have been going through a lot of ARMv8 documents, and I have a very basic question:

    -Can I take a Linux Kernel, compiled for a ARMv7 device, and run it on an ARMv8 device in Aarch32 execution mode?

    ( Lets assume that the two SOCs are identical…