• How to do from Secure(EL3) to Non-secure Exception level transition in ARMV8-A ?

    Hi all i trying do transition from EL3 to EL2 exception ,but after ERET of EL3 mode it change the mode to EL2 , but as soon as when it will execute first instruction of EL2 , then It goes to Exception ...

    This is happen for every secure to non secure transition…

  • What are the necessary preconditions to load a guest into EL1 from EL2?

    I have successfully moved from EL3 to EL2. After doing some initialization I am trying to move from EL2 into EL1 with a very simple guest image. My process looks like:

    • Map EL1 memory into EL2
    • Copy EL1 image to RAM
    • Initialize sctlr_el1 = 0x30d00800
      …

    • When are A32 state and A64 state determined?

      hi, expert

      i study ArmV8 architecture.

        On taking an exception to a higher Exception level, the Execution state either:

          • Remains unchanged.

          • Changes from AArch32 state to AArch64 state.

        i konw that…

    • How to deice debug target exception level of watchpoint on ARMv8 architecture

      Hello, everyone

      I'm new to this community.

      I'd like to ask many questions and want to help someone.

      Now I have some difficulties in understanding aarch64's watchpoint exception handling scheme.

      I found I can decide which exception level whachpoint…

    • how to return from exception generated by SMC instruction

      Hi,

      I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception is generated.

      I have written an exception…

    • ARM v8 Arch SCTLR bit field meaning

      Hi, I'm reading SCTLR bit fields and have 3 questions.


      1. In these bit fields (AFE, TRE, UWXN, WXN), there are comments like 'The AFE bit is permitted to be cached in a TLB.'

      I can't figure out what the meaning of 'permitted to be cached in…

    • How to trap Guest data aborts

      Hi,

      I am trying to understand if Guest OS data abort happens due to accessing some memory (e.g GIC distributor space) then is there any way I can route it to EL2 mode ?

      I looked into HCR_EL2 register bits and tried setting AMO bit but it doesn't help. I…

    • EL1 behavior when MMU is off

      Hi,

      I am facing issues with EL1 Guest OS.  I have enabled EL2 stage 2 page tables and set up all the virtualization registers {HCR_EL2, VTCR_EL2 and VTTBR_EL2 etc.}

      I am mapping my Guest OS memory to stage 2 tables but as I try to do "eret" from EL2…

    • ELn configuration in ARMV8

      Hi Experts,

      Does the EL3 and EL2 usage is the purely implementation specific or even though EL3 is implemented is it possible to disable EL3 and EL2 in software ?

      Regards,

      Techguyz

    • Reason Behind EL2 in non-secured state ARMv8

      Hi Experts,

      What is the reason behind allowing EL2 only in non-secured state in ARMv8 ?

      Regards,

      Techguyz