• How to do from Secure(EL3) to Non-secure Exception level transition in ARMV8-A ?

    Hi all i trying do transition from EL3 to EL2 exception ,but after ERET of EL3 mode it change the mode to EL2 , but as soon as when it will execute first instruction of EL2 , then It goes to Exception ...

    This is happen for every secure to non secure transition…

  • When are A32 state and A64 state determined?

    hi, expert

    i study ArmV8 architecture.

      On taking an exception to a higher Exception level, the Execution state either:

        • Remains unchanged.

        • Changes from AArch32 state to AArch64 state.

      i konw that…

  • In aarch32 state, what is the mechanism to switch to aarch64 in software?

    Dear sirs,

    I'm reading arm v8a specification. I found that when arm is in aarch32 state, only a few exceptions can switch to aarch64 depending on the configuration in the registers. the exceptions are as follows.

    abort, physical async abort, physical…

  • How to deice debug target exception level of watchpoint on ARMv8 architecture

    Hello, everyone

    I'm new to this community.

    I'd like to ask many questions and want to help someone.

    Now I have some difficulties in understanding aarch64's watchpoint exception handling scheme.

    I found I can decide which exception level whachpoint…

  • how to return from exception generated by SMC instruction

    Hi,

    I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception is generated.

    I have written an exception…

  • how to understand ARMv8 exception level1 secure/non-secure MMU?

    Hi Experts,

         ARMv8 MMU TTBRn_ELx registers are banked by exception level.

         In "DDI0487A_b_armv8_arm.pdf" page 1640, the controlling register of secure EL1&0 stage1 is TTBR0_EL1

         and Non-secure…

  • ARM v8 Arch SCTLR bit field meaning

    Hi, I'm reading SCTLR bit fields and have 3 questions.


    1. In these bit fields (AFE, TRE, UWXN, WXN), there are comments like 'The AFE bit is permitted to be cached in a TLB.'

    I can't figure out what the meaning of 'permitted to be cached in…

  • aarch64 Exception Level Sw itch from EL1 to EL0

    Hi Expert,

    I am working on a simple kernel and test it on Qemu which supports RasPi3. During the boot level. Ras Pi goes to EL3 level, and I set spsr_el3 to 1 and elr_el3 to kernel_main and then use eret to enter EL1 mode. My problem is I create a kernel…