IO coherency also allows device to access coherent memory space. The only difference I noticed is that cache stashing connects device directly with cluster, however, IO coherency transactions need to go through system interconnect.

Is the fabric topology in the DynamIQ cluster a conventional cross bar or a ring/mesh?

Is four the maximum number of big cores in a Dynamiq cluster? why is it? memory bandwidth? or soc routing concerns?

Is one big cluster (4 big + 4 little)  feasible in terms of routing? Is it preferable to have more smaller CPU clusters?

For a cluster…