• Cortex-A8 - accessing banked registers from monitor mode

    Note: This was originally posted on 20th March 2012 at http://forums.arm.com

    Hi Group,
    I am working on a Cortex A-8 Processor (ARMv7-a architecture). I am in the monitor mode and trying to access SP of the SVC mode.

    I know two ways I can do it:

    1) Using the…

  • how to enable am335x Monitor debug-mode

    Hi ,

    The monitor debug mode can be configured in DSCR, which is writable via APB interface for am335x. But,  I read the DRAR(MRC p14, 0, <Rd>, c1, c0, 0) and DSAR(MRC p14, 0, <Rd>, c2, c0, 0). Both of them are invalid value (both are 0).…