• ARM Cortex-R4F Re-entrant Example

    I was reading a post regarding re-entrant interrupts where you said:

    Re: Is there ANY Cortex core that supports reentrant interrupts?


    Hi Marcus, Cortex-R and Cortex-A processors does not have NVIC. Users (SoC designers) using these processors can use…

  • Division by non-power-of-2 hits into exception

    Hi there,

    I was using Codewarrior targeting Cortex-R4 CPU to build Firmware. When doing a division coprocessor was used and caused exception.

    Here is the division in C:

    u8 i, j = 8;

    i = j / 3;

    Disassembly:

    (u8 i, j = 8;)

    mov r5, #0x8

    (i = j / 3;)

    mov r1, #0x…

  • Cache maintenance and DMA

    Greetings ARM community,

    I have been tasked with cache maintenance.  The necessity popped up because of DMA issues on USB.

    As a quick (not perm solution) I used the invalidate all routine.  While obviously not nominal in anyway

    it does allow me…

  • Using shareable attribute in MPU configuration of Cortex R4

    Good day all,

    I'm working with a SOC with dual Cortex-R4 that comes with MPU.

    Due to the SRAM limitation and other restrictions, I'm not using any embedded linux or any other SMP RTOS.

    Currently I'm working on the optimization of the flow, so I'm…