• Regarding ADFSR and AIFSR in ARM Cortex-A9 MPcore

    Hello all,

    I was debugging an imprecise external abort in one of our product based on i.MX6q and came across a register - Auxiliary Data Fault Status Register

    readable and writable by the following instructions -

    MRC p15,0,<Rt>,c5,c1,0

    MRC p15,0,<Rt…

  • Cortex-A5 based processors

    Hi all,

    It is just out of curiosity that I wanted to see the chips based on Cortex-A5 core. I couldn't find much except some Atmel SAM5 or something.

    For the Cortex-A8, there seem a number of processors available from Texas Instruments, Freescale…

  • does different arm TRM revisions also have changes in Hardware?

    Hi

    I have an inquiry. our company is using Cortex-A9 quad Core. So in ARM website there are many technical reference manuals for the same in different revisions , such as:

    r2p0

    r2p2

    r3p0

    r4p0

    r4p1

    so what should i follow?

    or should i follow latest revision?

    or…

  • Dhrystone Testing on Cortex A9: disabling Prints increases the DMIPS.

    i am seeing an issue while doing Dhrystone test. i am using Dhrstone source code of version 2.1.

    when i run this source code on LINUX platform, i got DMIPS/MHz =1.6

    but there are some printing commands that prints variables used, when i disable them i got…

  • Basic tests on Cortex-A9, Cortex-A5x

    hello everyone

    our company in their products is using Cortex-A9, Cortex-A5x processors inside.

    i want to know same basic tests that i have to check to validate ARM Processors:

  • arm cortex a9 c++ support

    Hello,

    I'm new to arm cortex a9. how good does the compiler support C++11 or C++14 on bare metal? where can i find the latest compiler?

    I use Xilinx Zynq 7010 SoC, which comes with a Dual ARM® Cortex™-A9 MPCore™ with CoreSight™. (…

  • Cortex A9 CPU self-tests

     

    Hi!

    I am currently working in a project with a Freescale i.MX6 (Cortex A9) board. The system has to be certified against the ISO 13849 standard and my job is to implement software diagnostics in accordance to ISO 13849.

    Now my problem is that ISO…

  • code compile using -mcpu for ARM platform

    When using gcc to compile c code for ARM platform, we set object platform by using:

         -mcpu = xxxxxx

    To what extent will that affect results of compiling ?

    For example:

         -mcpu = cortex-a8

    and

         -mcpu = cortex…

  • share memory between core0 (linux) and core1 (bare-metal)

    Hello,

    i want to use the arm cortex a9 to share memory between both cores. are there any examples online?

    Thanks,

    Mike

  • Cortex-A9 core registers

    In RTL code of A9mp platform provided by ARM, I see that almost all registers are renamed and are out of order(There are registers named R0-R55). This make it quite difficult for me to debug some problems.

    So how can I match them with R0-R14, especially…

  • Is it possible to read the raw L1/L2 cache data and tag bits on the Cortex-A9?

    I've been digging through the Technical Reference Manual (TRM) for the Cortex-A9 and so far it seems that it's possible to gather data about events such as hit and miss rates, but there doesn't seem to be anything on reading the raw data and tag bits…

  • Minimum MMU table size on ARMv8 to map 4GB memory space, in AArch64 mode

    On ARMv7 Cortex-A8/9/7, to map 4GB memory space, the minimum MMU table size is 16 KB(section mapping). Any possible to map 4 GB memory space with 16 KB MMU table, on ARMv8, AArch64 mode?

  • De-merits in using Cortex A9 for single core processor

    Hi Experts,

    A8 is meant for single core and A9 is for multi-core based.

    Consider in case of SoC is build with single core of A9 and A8 how we could compare both in terms of some metrics/parameters like power/speed ?

  • ARMv7 performance monitor:how to get L2 cache refill?

    The processor is Samsung's Exynos 4210, ARM Cortex-A9, I want to know whether it supports the L2 cache refill or memory access event?

  • 8-byte stack alignment for ARM Cortex-A9

    Hello everbody,


    as i have written before in "Compability between architecture ARMv5TE and ARMv7-A", we want to change our Platform-Processor from ARM946E-S to an ARM Cortex-A9. The next Point in our risk disclosure ist the stack alignment.

    Our…

  • How to use the amba bus?

    Hello,

    i have the Zedboard which contains arm Cortex-A9 cortex with the amba bus..

    i have searched a lot but I probaly miss the point.

    i want to use data and to transfer  data from the processing system to the programable logic section via the amba bus…

  • I NEED INFO ABOUT THE ARM CORTEX-A9 ASAP!!

    Description of the register architecture (preferably with pictures), including names, sizes and intended uses of all registers

    Description of all instruction formats

    Description of all addressing modes


    THANKS

  • Cortex-A9: Eviction of dirty line from the region marked as Only "Inner Cacheable" from L1 cache - will if be allocated into L2?

    Hello,

    Consider following scenario:

    1. A 4 KB page starting @0x80000000 is marked as Normal Memory, Inner Cacheable, write-back, non-shareable, non-outer cacheable, L2 is inclusive cache.
    2. Now, the s/w writes to the first word in the page. Let's assume valid…
  • Regarding mismatched memory attributes and cacheability

    As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ

    My question is specific to the case when it is only the cacheability…

  • Issue about Cortex-A9 Dhrystone performance

    Hi,

    We found the following document on Cortex-A9 performance.

    List of ARM microarchitectures - Wikipedia, the free encyclopedia

    Which claims 2.5 DMIPS/MHz per core for Cortex-A9 2GHz@2 core. However, our Dhrystone result on Cortex-A9 1.2GHz@2 core only showed…

  • Cortex-A9 Branch prediction to speculative execution

    Hi,
    I am building a cycle accurate simulator for the Cortex-A9 core, and so far I constructed most of the stages of the pipeline.

    However I am having trouble placing something that is not clear in any source I have found.

    Most diagrams show the prefetch…

  • How to switch off 2nd core for Cortex-A9

    I am using dual-core Cortex-A9 in a project where 1 core is enough.

    How to switch off another unused core?

  • Cortex-A9 secondary boot Procedure

    I am trying to enable SMP  functionality  for our custom target having a dual core.

    Below is my understanding w.r.t Basic ARM secondary CPU boot address:

    a. The secondary CPU is provided with some registers (named like BOOTUP REG) to keep the…

  • What is the lowest frequency I can run ARM Cortex-A9 Processor ?

    What is the lowest frequency I can run Cortex-A9 Processor ?

  • Clean Whole Cache on Cortex-A9

    I am doing some benchmarking and I need to clear the cache before each test. I have this example here:

    Caches and Self-Modifying Code

    However, I just want to clean the whole cache. Is there an easy way to do that? I do not need to know the start and end…