Hi ARM expert,
I am trying to use generic timer, but seems the generic timer wasn't enabled. My steps are:
4. Read CNTP_CTL in a loop, wait for bit…
Hello everyone.
I am new usage of Allwinner A20.
I read in Cortex-A7 specification, that it have DSP & SIMD extensions.
And if there are digital processing unit in processor, can i use it? Can i drop on it some code, as any other DSP? And if yes, will…
Hi all,
I'm trying to boot Linux on my hypervisor like environment.
In booting process, unexpected hyper trap was occurred and became hyp mode.
In hyp mode, the Hyp Syndrome Register (HSR) value is 0x93830006.
According to the manual, this meant "Fault…
I was wondering about LDRT when the operand is rrx'd. Which where does the carry-bit come from?
LDRT{<c>}{<q>} <Rt>, [<Rn>], +/-<Rm> {, <shift>}
RRX Rotate right one bit, with extend. Bit[0] is written to shifter_carry_out…
Is there a reason why banked registers SP and LR can't be accessed as r13_<mode> or r14_<mode>, but
one has to use SP_<mode> or LR_<mode> instead? It makes macros and inline assembly difficult.
In document (ARMv7-A/R ARM Issue…
Is there something special in the instructions ADD (SP plus register, ARM) and SUB (SP minus register)?
I didn't find anything different from the basic ADD (register) and SUB (register) except the documentation:
<Rd> The destination register…
In the SSAT instruction description it says:
ASR #32 Arithmetic right shift by 32 bits, permitted only for encoding A1. Encoded as sh = 1, immsh = 0b00000.
ASR #32 Arithmetic right shift by 32 bits, permitted only for encoding A1.
Encoded as sh = 1, immsh = 0b00000.
What does that mean?
Isn't ASR #32 the same as ASR #31?
I understand that it shifts (with "sign…
In some instruction descriptions there are calls to SignedSatQ (directly or indirectly).
The pseudocode for SignedSatQ:
(bits(N), boolean) SignedSatQ(integer i, integer N) if i > 2^(N-1) - 1 then result = 2^(N-1) - 1; saturated = TRUE; elsif i < -(2…
(bits(N), boolean) SignedSatQ(integer i, integer N)
if i > 2^(N-1) - 1 then
result = 2^(N-1) - 1; saturated = TRUE;
elsif i < -(2…
In quite many instruction descriptions it says:
if d == 15 then UNPREDICTABLE;
What does this mean?
Can the instruction really work in some unexpected way in each such case or what?
I guess if I use a bit-reversing instruction on PC I should expect that…
The registers in the instructions are usually 'named' Rn, Rm, Rd, ...
Is there some deeper meaning in the names?
Usually Rd seems to mean 'destination register'
Sometimes Rn is the only operand, sometimes it's Rm. Also the place in the instruction…
I'm seeing Cortex-A7 cycle-timing table here :
http://hardwarebug.org/2014/05/15/cortex-a7-instruction-cycle-timings/
For example,
VADD.F32 Dd, Dn, Dm takes 2 cycles
VADD.F32 Qd, Qn, Qm takes 4 cycles
same goes for VMUL..
Is this really the case…
Still more instruction things giving me head ache.
This time it's the MUL-instruction.
What the heck means:
Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do…
Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination
register. These 32 bits do…
Are there differences between coprocessor instructions and instruction2:s?
I mean:
MCRR vs. MCRR2
MRRC vs. MRRC2
MCR vs. MCR2
MRC vs. MRC2
LDC vs. LDC2
STC vs STC2
I didn't find any differences in the encoding except the condition code, and no differences in…
Hi,
Where i can find step-by-step instruction how to init SMMU PA->IPA translation? (With procedure description)
(i checked ARM ® System Memory Management document, but i was not found exact instruction how to setup correct translation).
I have ARM…
I use a Cortex-A7 board and write start up code.
I try to use Security Extension.
I use `smc` instruction and make cpu mode monitor mode.
In the monitor handler, I tried to changed stack pointer value for calling other functions.
But after execute `ldr sp…
I just got a raspberry pi 2 and I'd like to play with Trustzone.
People on the Raspberry forum http://www.raspberrypi.org/forums/viewtopic.php?p=697474#p697474 explained me how to
get my hand on the boot of the 4 core A7 CPU, and I managed to boot…
On ARMv7 Cortex-A8/9/7, to map 4GB memory space, the minimum MMU table size is 16 KB(section mapping). Any possible to map 4 GB memory space with 16 KB MMU table, on ARMv8, AArch64 mode?
According to related manuals, I see that Cortex-A7 is able to send 8-bits, 16-bits, 32-bits, and 64-bits exclusive access.
I'm wondering that if it's able to send a 128-bits exclusive access or not.
Performance (DMIPS/CoreMark/SpecInt, etc.), Power and Area comparison on an apple-to-apple basis? Thanks a lot!
In ARM Cortex-A7 platform which includes L1 and L2 level caches，I start cache setup flow as follows:
1. Enable SMP bit and disable MMU.
2. Disable I cache in L1, and invalidate it , then enable it.
3…
Hi ,
I am working on Arm for the first time . I am trying to implement a scenario to boot 4 cores parallel . I have few queries here
--> Reset lifting procedure for 4 cores ? how exactly they should behave ? (any doc also fine…
Hello,
I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I the system there will be a cortex A7 master(64bytes cache line). My question is: in case of such transaction (WriteLineUnique with 128bytes…