Hi everybody!!

I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).

In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num…

Hi, I am using imx6ul board which has cortex a7 processor. I am using ffmpeg .s files which has assembly code to integrate into our project to speed up the code.  Here is the ffmpeg code in the file mdct_neon.S.

#include "asm.S"
.fpu neo…

I'm thinking about using a cortex-a7 in "bare-metal" where I don't need much memory, so i'd like to avoid using external memory.

The CPU boots from an external 4MBytes SPI NOR FLASH chip.

It has 512 KBytes of L2 cache and 32 KBytes…

Hi experts!

As you know, power efficient arm like cortexA7, A53 has in-order pipleline.
However as far as I understanding, Barriers like dmb, dsb, isb are related with out-of-order memory access.
But barriers are even used in in-order cpus.
What is for?
Can…

I am trying to run two Cortex-A7s in AMP configuration with Linux running on one core (SMP disabled) and baremetal/RTOS running on other core. I am having difficulty in setting up SGIs (IPIs) between the two cores. I am at a point where both of the cores…

Hello,

i was wondering if the voltage levels for dvfs states are fixed at the design time. For example for Cortex A7 or A15. Is this information available?

Thank you.

Hi,

I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"

we can see several information regarding a cache line. Those are:

1. Current data in cache

2. its 4-bit MOESI state,

3. Outer Memory Attribute

4. its tag

5. NS State.

However…

hi, experts:

I found ACTLR register definition is different between Cortex-A7 and Cortex-A9.

I have some questions about out cache concept in Cortex-A7.
1. Some program disable outer cache by setting ACTLR[1] = 0.

   So, is it only available with Cortex-A9…

What can be accessed by MRS/MSR in user mode?

In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1):

I wonder if the bit 22 has some function in instructions like LDRH, STRH, LDRSBT, LDRD, ... (bits 27, 26, 25 = 0, 0, 0)?

I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found

an answer to in ARMv7-A/R ARM Issue C.

How is this special?

When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.

But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......

And, if…

If a region is marked as non-cacheable, will the CPU also first check the cache when CPU want to access the region?

In cortex-A7 spec, it says" the core hardware will check all instruction fetches and data reads or writes in the cache, although obviously…

Where can I find the cortex-A7 related 8 stages pipeline docments?

I have found some docments about this but all are too brief, so I want ask where can I find the detailed docments?

In cortex-A7 it has 8 stages pipeline, so PC's value is current program address add how many bytes?

Where can I find the docments about how the ARM cortex-A series pipeline works?

Such as the first step of the pipeline do what and the second step of the pipeline do what, and also the Cortex-A series has different pipelines(such as cortex-A7 is different…

Cortex-A7 structure can support max to 4 cores, I want ask the 4 cores have 4 part copy of the registers(37 registers * 4)?

In other words, each core have the same 37 registers or the 4 cores share the 37 registers?

For example, in ARM's related docments says that cortex-A7 support max to 4 cores and cortex-A8 support only one core, and the same time cortex-A7's pipeline is not the same with cortex-A8's pipeline. I want ask the cortex-A7's pipeline is for all the…

What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean?

In ARM's white paper(about the cortex-A7 and cortex-A15) says as follow:

I want ask the in-order and out-of-order mean what?

Cortex-A7 pipeline is non-symmetric, what does this attribute mean?

My understand is that cortex-A7 pipeline's five entries does not have the same two, in the contrary, the cortex-A15 have the two entries are the same.

Cortex-A7 contains MMU I want ask the MMU is contained in which part of the diagram?

Because in the CA7 block diagram doen't have a MMU part, so I think it is contained in which part.

What's the single cycle Load-Use in ALU mean?

This is in the follow picture:

The cortex-A7's pipeline support dual-issue, so I want to ask what's the dual-issue mean?

I find some answers say that dual-issue means that the cortex-A7 can issue two instructions per clock.

But in the cortex-A7's pipeline diagraph, it has integer…

in cortex-A series, most core has the BITC(branch target instruction cache). It is contained in the prefetch unit.

Branch Target Instruction Cache

The PFU also contains a four-entry deep Branch Target Instruction Cache

(BTIC). Each entry stores up to two…