1. What is the input & output of system counter? What is it's purpose? How to start/stop it?
2. What is the input & output of Physical counter? What is it's purpose? How to start/stop it?
3. What are the differences between Physical Counter &…

We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core.

While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly ordered (Device-nGnRnE memory type) and then witness…

excuse me for my English!!!

i want to write bare-metal startup code in 32-bit mode for LS1043A-Rdb.it is having V8 A53 core.

i have bare-metal 32bit(AARCH32) code for xilinx processor(which is of V8,A53core).How much of that code is useful to write code…

******************************************************************************/
/*****************************************************************************/
/**
* @file translation_table.s
*
* @addtogroup a53_32_boot_code
* @{
* <h2> translation_table…

can you please tell me how to boot up a processor in 32 bit mode for Armv8, A53 core using baremetal code?

how can i know it is booted in 32bit mode?

Thanks.

Hello all,

The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC-DED) and for L1 D-cache dirty (which is SED-SEC) triggered…

hi,

on a cortex a53, I would like to get the best of both worlds. Having dcache enabled but no page walk in case of a miss.

I want no memory protection because we manage the whole system ( kind of baremetal processes)

Is there a way to tell the mmu controller…

Hi,

From a previous question I got that setting the EPDx bits from the TCR_ELx register to 1 will disable table walk.

Good starting point. But, should I access the same memory location again, it won't be in the TLB cache.

How to work around that?

Where is the register definition of the CurrentEL register ?. I cannot seem to find it in the ARMv8A programming model guide or the Cortex-A53 TRM.

. How does the PSTATE bits map to CurrentEL ?

I read somewhere that a CurrentEL value of 0x4 denotes EL1…

Dear experts,

 I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation.

Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached), Can other cores  get the right data at VADDR ?

For…

Please clarify that with me... With

"The current Program Counter (PC) cannot be referred to by number as if part of
the general register file and therefore cannot be used as the source or destination
of arithmetic instructions, or as the base, index…

Hi all,

I am trying to access the system control register in my ARM C program. The code (with heading 64 bit) I used is presented below. However I got the following error message during compilation.

/tmp/cc7Dc236.s: Assembler messages:
/tmp/cc7Dc236.s:31…

I come across strange issue with Optimization setting O2 and O3 option my code will not work due to PC corruption, with O1 and O0 code woke fine, our target procesor is Arch64bit Cortex-A53. how to fix this issue. my i know what is the limitation of Heap…

Hello experts,
I am working on a53 core in which I am not able to run string library functions like memset, memcpy etc. I have included the string.h library also but it is generation an exception. The same code works on the a15 core without any modification…

Hello,

I'm trying understand the capabilities of both the cortex R5 and A53 but stuck at the point where i want to communicate to each core (A53 - Quad Cores and R5 - 2 Cores) in parallel. Can some one help me in understanding this or point to the related…

Hi,

I am triggering PPI or SGI interrupt on gic500 which will then communicate with CA53 over cpu interface and interrupt routine will be executed. 

After interrupt routine is executed, we can write to cpu interface End Of Interrupt Register to "clear" interrupt…

Our project only wants 2 cores to support NEON for cost reasons. How can I do this?

1. Can a single cluster be done?

2. Cut into 2 clusters, each with 2 cores. What is the difference between the performance of ARM HMP scheduling 4 cores and the performance…

Hello everyone,

I'm trying to wrap my head around the MMU configuration for Cortex A53 armv8 architecture (AArch64). Specifically, I'm programming for Raspberry Pi 3 (Bare Metal).

I've successfully setup the page tables for two levels covering…

Hello everyone,

I'm experimenting a bit with MMU after understanding its core principles. Specifically I can successfully enable it with an identity mapping for TTBR0 (no TTBR1) on a Raspberry Pi 3 (Cortex A-53, ARMv8 AArch64).

The next step I wanted…

when we says "Cortex-A53 processor simplifies the coherency logic by downgrading memory to non Cache able if it is marked as Inner Write-Through or outer Write though" what is excatly this means ..Is CA53 treats WT memory as non cache able ?…

Hi All,

my situation is, I have to zeroize complete caches in ARM-v8 (Xilinx Ultrascale+ Device). Zeroise or set every line to constant values.

Does anybody know how can I solve this?

Thanks in advance.

Hi all,

Recently I encountered a problem. During CA53 bootup stage, PC will transfer a small executable program to the target platform via USB and then give the control to that program, which will first do PLL init. Strange point is that the PLL init…

Hi,

     Linux Kernel 4.9

     Processor a53

      SMP 64 Bit linux image

Issue seen:- Ethernet interrupts are seen arriving only on core0 ONLY, though core0 is completely occupied by other interrupts.

moving ethernet interrupts to other core via smp_affinity…

I have been trying to do a preemptive context switch on interrupt on the Cortexa53 but it isn't working can anyone spot an error in the code.

The code has no FPU use so it is supposed to be just a lazy save and restore registers.

The restore section…