• Does ARMv8-A has VC_CORERESET or something similar?

    Hi All.

    Does ARMv8-A has something similar to VC_CORERESET bit in Debug Exception and Monitor Control Register of ARMv8-M ; which enables halt on reset vector on warm reset?
    Or is there any other method to halt the ARMv8-A core in reset vector?

  • performance of floating point

    hi.

    I have a question about floating point performance relative with fpsr register.

    When i initialize hardware, there is floating point exception(inexactly floating-point exception).

    I did not set fpcr.IXE=0, so fpsr.IXC is set. not occur exception.

    …

  • [Cortex-A53] Exception Syndrome Register - Exception Class

    Hi,

    I'm searching for the documentation for the exception classes in ESR_ELx. But currently couldn't found any information.

    Want to port my bare-metal applications to AArch64. I own a PINE64 Rock64 (quad core Cortex-A53) board, which I want

    …

  • Cortex A53 Bare metal booting have FIQ exception. How to debug?

    Hi

    I study coresight test with cortex A53 CPU.

    I get FIQ interrupt when I running helloworld test in ini_libc function. But I don't known why.

    I use gcc-linaro 4.9 toolchain : aarch64-none-elf-gcc  with glibc 2.14

    Set CPU config pin aa64naa32 to 1…

  • A53 Erratum 820719 missing from official ARM errata document list

    There is a reference to erratum 820719 in the NXP S32V Errata list but I can't seem to find any reference to this erratum anywhere in ARM documentation. Is this erratum still valid?

    Excerpt from S32V Errata document (refer: https://www.nxp.com/docs…

  • Problem in understanding behaviour of GCC compiler (aarch64-none-elf-gcc) on Neon intrinsics for ARM cortex a53

    Hi,

    I am using IDE Xilinx SDK 2019.1 for my application and running it on ARM cortex a53  processor with Neon and floating point engine support available. I am working on a bare metal application.

    The problem I am facing is that, I am unable to understand…

  • compiler optimization options for ARMv8 GCC compiler on ARM cortex a53 (bare metal application)

    I am using ARMv8 GCC compiler(aarch64-none-elf-gcc) for my bare metal application on ARM cortex a53. I am using neon intrinsics with plain C in my code so I would like to ensure to use all optimization option available for this compiler.

    I tried -mfpu…

  • Optimization of Neon Intrinsics on ARM cortexa53

    I am using ARMv8 GCC compiler and I would like to optimize Neon Intrinsics code for better execution time performance. I have already tried loop unrolling and I am using look up table for the computation of log10. Any ideas?

    Here is the code:

    static inline…

  • Resetting GIC by SW?

    Hello,

    we have a board using Armada 3720 SOC, which contains two Cortex-A53s and one Cortex-M3 used as secure-coprocessor. The interrupt controller is GIC-500.

    The M3 has access to all registers that A53 can see. The first A53 has RVBAR at 0xffff0000 where…

  • [ArmV8] [Cortex-A53] [PMU] PM_CCNTR to measure cpuload

    Dear Experts

    I am working on a target that contains quad A53 cores operating at 1GHz. The operating system idle loop contains WFI inline assembly instruction. I know that the Core Clock halts during the WFI instruction which can be seen on the PM_CCNTR…

  • ARMv8 memory ordering

    In the ARM Architecture Reference Manual issue D.a (ARM DDI 0487D.a) section K11.3.1 "Acquiring a lock" has the following example code:

    AArch32 
    Px 
            PLDW[R1]                     ; preload into cache in unique state 
    Loop 
            LDAEX R5, [R1]               ; read…

  • Obtain CPU Temperature in Kernel

     Dear All,

    I am using a raspberry pi B+ that uses a Broadcom BCM2837 SoC with an ARMV8  processor. I want to get the cpu temperature in a Linux kernel file. Like in x86, I can use rdmsr_on_cpu function to load the temperature from MSR_IA32_THERM_STATUS register…

  • Which processor has the most cores?

    Which arm processor has the largest number or cores?

  • How to get the secure(or non-secure) state on Cortex-A53?

    Could anyone give me the code to get the current secure state?

  • Barriers in in-order cores like cortex-A53, A7

    Hi experts!

    As you know, power efficient arm like cortexA7, A53 has in-order pipleline.
    However as far as I understanding, Barriers like dmb, dsb, isb are related with out-of-order memory access.
    But barriers are even used in in-order cpus.
    What is for?
    Can…

  • Cannot access EL1 resources from EL3 or secure world on armv8.

    The working secerio is that I'm testing OP-TEE on a Hikey board(Cortex-A53, armv8), and they use arm-trusted-firmware(see https://github.com/linaro-swg/arm-trusted-firmware) to be the monitor running in EL3.

    I'm trying to access some resources in EL1…

  • Trustzone and Hardware virtualization support

    Hello,

    I am looking for a development board that has an open Trustzone and hardware virtualization support. Do the Juno boards support this?

    Looking around the ARM A72/57/53 chips all support Arm Trustzone and have hardware virtualization support, however…

  • How to modify the value of AWCACHE [3:0] and ARCACHE[3:0] in AXI?

    hey,

    How to modify the value of AWCACHE [3:0] and ARCACHE[3:0] in AXI?

    in baremental driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x00,

    but in linux driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x01,

    can anybody tell me…

  • Where is hardware interrupt latency documented for the ARMv8 Cortex-A53?

    Need specific references to the hardware interrupt latency for the ARMv8 Cortex-A53.  interrupt latency from when an interrupt is triggered to when the ISR is initially invoked, but not including operating system, kernel, or application latency.

    …

  • how to return from exception generated by SMC instruction

    Hi,

    I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception is generated.

    I have written an exception…

  • MOESI state encoding of Cortex-A7

    Hi,

    I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"

    we can see several information regarding a cache line. Those are:

    1. Current data in cache

    2. its 4-bit MOESI state,

    3. Outer Memory Attribute

    4. its tag

    5. NS State.

    However…

  • why there are 4 cores per cluster in ARMV8 architecture

    Hi experts,

    I want to knows why there are 4 core cores per cluster in ARM big.Littte architecture?

    Is it possiable if we make more cores per cluster? if not, what is the limitation?

  • I am very new to ARM, still understanding the terminologies. What is the difference b/w the Cortex family and the x-gene?

    Where can i get a list of all these family of ARM processors and their differences

  • Power Management Options in Cortex A

    Hi Experts,

    Whether the ARM provides the power management controller inbuilt in the cortex A5x processors or it provides signal pins suitable for easy integration with the power management controllers ?

  • How SMMU will override the memory attribute of the master which have MMU/MPU embedded?

    For example, one M4 is a client of SMMU, and its MPU had been configured to map some memory(MEM_A) as inner outter write-back, how the configureation of SMMU context transcation table will affect the access attribute, say, the transcation table mark …