• Data Abort Exception in A53

    Hello,

    I am working on Cortex-A53  and using Cortex-A53 DSM Model in my design. We are getting Data Abort exception on a read to ROM address and ESR_EL3 register showing its a DECERR External error. MMU and Cache both are not enabled at this point where…

  • MMU: force identity mapping without pages?

    hi,

    on a cortex a53, I would like to get the best of both worlds. Having dcache enabled but no page walk in case of a miss.

    I want no memory protection because we manage the whole system ( kind of baremetal processes)

    Is there a way to tell the mmu controller…