• Trustzone and Hardware virtualization support

    Hello,

    I am looking for a development board that has an open Trustzone and hardware virtualization support. Do the Juno boards support this?

    Looking around the ARM A72/57/53 chips all support Arm Trustzone and have hardware virtualization support, however…

  • Power Management Options in Cortex A

    Hi Experts,

    Whether the ARM provides the power management controller inbuilt in the cortex A5x processors or it provides signal pins suitable for easy integration with the power management controllers ?

  • CPUID information about ARMv8 core

    Hi experts,

    I want to know if there are CPUIDs information in CHI interface about IP A53/57 Mpcore? and can CCN504 transfer the CPUIDs to Slave device? for example, AXI_USER？

    Thanks.

  • Cortex-A72 and Cortex-A5x series boards

    Hi Experts,

    Is there any sample development boards available on Cortex-A72/5x series ?

    Regards,

    Techguyz

  • How to measure program execution time in ARM Cortex-A53 processor?

    Hi,

    I was using following method to read clock in cortex-a15:

           static void readticks(unsigned int *result)

            {

                struct timeval t;…

  • If non-secure world pass to virtual address (allocated by malloc or mmap) and ttbr value, how to find valid physical address in secure-world

    First sorry my english writing level. :-)

    In non-secure world using android system(linux kernel).

    I use big.little core Cortex-A53, Cortex-A57

    I was tested to 2case.

    previous stage.

         1. Linux allocation memory using(malloc or mmap)

    …

  • Does CCI-400 guarantees cache coherency between secure and non-secure worlds?

    Hi Experts,

    I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC.

    While multi-core testing, I'm facing some wired problem on my world shared memory mechanism.

    When I run world shared memory test on a single core (using affinity), it works…

  • Armv8 Memory Mapping

    I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which I can determine the memory address being accessed…

  • Using an external clock - experts only

    I'm looking to emulate a 6502 on the ARM but I would like to make it cycle accurate so I need some way to interface to an external clock. I can't rely on an internal clock as there are external components that will rely on the external clock as well and…

  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

    Hi, 

    I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

    The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

    There is no L3 cache. So the memory…