• Cortex-A53 direct access to cache: How are instructions encoded in the L1 I-cache?

    The TRM for the Cortex-A53 has a section on direct access to various internal memories, including the L1 I-cache and D-caches. I'm successfully able to dump both tag and data for the I-cache and D-cache, but I'm having trouble making sense of the I-cache…

  • How to do cache invalid on Cortex-A53?

    hi,

         I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid.

         Could you give me any suggestion about cache invalid? Thanks!

         The program…

  • Can we run the Cortex-A53 cores at different clock speeds ?

    Dear ARM Group,

    Can we run the A53 cores at different clock speeds?

    if YES,  How does it effect the complete A53 (L2 cache etc) and system?

    if NO,  What are the constraints ?


    could you please give a detailed description on this?


    Thanks,

    Ravinder…

  • Does CCI-400 guarantees cache coherency between secure and non-secure worlds?

    Hi Experts,

    I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC.

    While multi-core testing, I'm facing some wired problem on my world shared memory mechanism.

    When I run world shared memory test on a single core (using affinity), it works…

  • shareable domain and cache policy problem

    Hi,

    I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE architecture. I find some articles that telling L1 and…

  • when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thanks a lot！

    when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thank's a lot！

  • shareability attribute for armv8 cortex a-53

    Hi,

    I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

    My question is how should I interpret the shareability domain: inner, outer…

  • Cortex A53 : Cache policy setting

    Hi,

    Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? 

    I'm enabling the caching using the SCTRL register and in the MMU configuration table, I'm setting the memory…

  • Cortex-A53 Cache protection

    Hello all,

    The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC-DED) and for L1 D-cache dirty (which is SED-SEC) triggered…