• how to return from exception generated by SMC instruction

    Hi,

    I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception is generated.

    I have written an exception…

  • why there are 4 cores per cluster in ARMV8 architecture

    Hi experts,

    I want to knows why there are 4 core cores per cluster in ARM big.Littte architecture?

    Is it possiable if we make more cores per cluster? if not, what is the limitation?

  • Why the address width of MMU-500 is different with Cortex-A53/57?

    I find the description below from MMU-500 TRM.

    Address width

    The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address width is 48 bits and the width of the AC address

    bus…

  • I am very new to ARM, still understanding the terminologies. What is the difference b/w the Cortex family and the x-gene?

    Where can i get a list of all these family of ARM processors and their differences

  • How to measure program execution time in ARM Cortex-A53 processor?

    Hi,

    I was using following method to read clock in cortex-a15:

           static void readticks(unsigned int *result)

            {

                struct timeval t;…

  • ARMv8 EL1 MMU

    Hi,

        I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1.

    I am not able to set sctlr_el1.M bit when ever i try to set this bit the instruction won't complete. I think it…

  • shareable attribute in armv8

    Hi Experts,

                        I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different.

    I could…

  • Armv8 Memory Mapping

    I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which I can determine the memory address being accessed…

  • What's the relationship between exclusive access and memory cacheable in Cortex A53?

    Hello community and experts,

             I am doing an experiment on Cortex-A53 which executes some exclusive access instructions such as 'ldaxr'.

             When I config memory to Normal type+cacheable, 'ldaxr' can execute well. But if I config memory to Normal…

  • About watch point debug excption on Cortex-A53

    Now we are researching watch point function on A53. We simply write a driver, hook debug exception handler aml_watchpoint_handler instead of default watch point handler.

    In our watch point handler, we first disabled watch point control, then handle debug…

  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

    Hi, 

    I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

    The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

    There is no L3 cache. So the memory…

  • ARMv8: strongly ordered memory and exclusive access

    We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core.

    While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly ordered (Device-nGnRnE memory type) and then witness…

  • could anybody help me to write a bare metal startup code for LS1043A (ARM V8,A53)in 32bit(AARCH32)mode

    excuse me for my English!!!

    i want to write bare-metal startup code in 32-bit mode for LS1043A-Rdb.it is having V8 A53 core.

    i have bare-metal 32bit(AARCH32) code for xilinx processor(which is of V8,A53core).How much of that code is useful to write code…

  • help me to understand this assembly program for configuring MMU for ArmV8,A53. 

    ******************************************************************************/
/*****************************************************************************/
/**
* @file translation_table.s
*
* @addtogroup a53_32_boot_code
* @{
* <h2> translation_table…

  • Could anybody tell me how to boot up a processor in AARCH32 bit mode in Arm V8 and A53 core?

    can you please tell me how to boot up a processor in 32 bit mode for Armv8, A53 core using baremetal code?

    how can i know it is booted in 32bit mode?

    Thanks.

  • ARMv8-A CurrentEL Register Definition

    Where is the register definition of the CurrentEL register ?. I cannot seem to find it in the ARMv8A programming model guide or the Cortex-A53 TRM.

    . How does the PSTATE bits map to CurrentEL ?

    I read somewhere that a CurrentEL value of 0x4 denotes EL1…

  • Multi core L1 cache coherent

    Dear experts,

     I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation.

    Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached), Can other cores  get the right data at VADDR ?

    For…

  • indirect branches in ARMv8

    Please clarify that with me... With

    "The current Program Counter (PC) cannot be referred to by number as if part of
    the general register file and therefore cannot be used as the source or destination
    of arithmetic instructions, or as the base, index…

  • code is not working for optimization setting O2 and O3 for Arch64bit Cortex-A53 process

    I come across strange issue with Optimization setting O2 and O3 option my code will not work due to PC corruption, with O1 and O0 code woke fine, our target procesor is Arch64bit Cortex-A53. how to fix this issue. my i know what is the limitation of Heap…