• how to return from exception generated by SMC instruction

    Hi,

    I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception is generated.

    I have written an exception…

  • How to measure program execution time in ARM Cortex-A53 processor?

    Hi,

    I was using following method to read clock in cortex-a15:

           static void readticks(unsigned int *result)

            {

                struct timeval t;…

  • brk instrustion

    Hi arm experts,

        I wrote some simple C functions to check if the result of memcpy is expected after enable MMU and data cache on Cortex-A53. The assembly (got by disassembling with aarch64-none-elf-objdump) of the one of these functions…

  • shareable attribute in armv8

    Hi Experts,

                        I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different.

    I could…

  • A53 preload mechanism

    Hi,

    I am reading the A53 MP Core doc.

    My question is related to instruction preloading in aarch64.

    In case of a very large block of code with no function calls, I want to make sure the L1 cache is always filled.

    Question 1:  Will the PLI instruction first…

  • ARM cortext A53 Physical Address Flush

    Since ARM caches are physically indexed is there any way to flush based on the PA? I know I can get the set, but what about the way? If I am flushing from L1 would I have to flush all ways in L1 and then L2 assuming there is no L3 to get to system memory…

  • System level Implementation of Generic Timer in Cortex A53

    Hi,

    Im new to ARM. Im learning generic timers in cortex a-53. I wanted to know whats the meaning of "system level implementation" of Generic Timer and "PE implementations" of the Generic Timer.  How is it different from Generic timer…

  • indirect branches in ARMv8

    Please clarify that with me... With

    "The current Program Counter (PC) cannot be referred to by number as if part of
    the general register file and therefore cannot be used as the source or destination
    of arithmetic instructions, or as the base, index…

  • How to access the system control register?

    Hi all,

    I am trying to access the system control register in my ARM C program. The code (with heading 64 bit) I used is presented below. However I got the following error message during compilation.

    /tmp/cc7Dc236.s: Assembler messages:
    /tmp/cc7Dc236.s:31…

  • code is not working for optimization setting O2 and O3 for Arch64bit Cortex-A53 process

    I come across strange issue with Optimization setting O2 and O3 option my code will not work due to PC corruption, with O1 and O0 code woke fine, our target procesor is Arch64bit Cortex-A53. how to fix this issue. my i know what is the limitation of Heap…

  • To run library functions on arm a53 core

    Hello experts,
    I am working on a53 core in which I am not able to run string library functions like memset, memcpy etc. I have included the string.h library also but it is generation an exception. The same code works on the a15 core without any modification…

  • Barrier after access to memory mapped register?

    Hi,

    Iam wondering if it makes sense to have a memory barrier after access to a memory mapped register. I looking at a driver, unfortunately not open source, that has a memory barrier after a read from the interrupt status register of the peripheral when…

  • Cortexa53 AARCH64 context switch

    I have been trying to do a preemptive context switch on interrupt on the Cortexa53 but it isn't working can anyone spot an error in the code.

    The code has no FPU use so it is supposed to be just a lazy save and restore registers.

    The restore section…