Hi ,
If I generate the elf file from the Default bootcode and pagetables , I get a very small size but
after mapping the Stack pointer to SRAM , I am getting a huge HEX file.
Here is the loader file code
============================================…
Howdy, I was trying to find some basic performance benchmarks for a couple of different ARM cores: The Arm 926EJ-S, Cortex A9, and the Cortex M7.
I am looking for primarily DMIPS (per MHz or a form that requires me scaling to my specific chip is fine…
Hi experts,
I am recently developing some bare-metal code for a Cortex-A57 Aarch64 on QEMU (Virt platform) for playing with the Virtualization Extension. I first used one core and I developed a bootloader from scratch that switches the execution from…
Hi Experts,
I have a question about "STP" instruction in Cortex-A53.
STP W6, W6, [SP, #20] --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted.
I don't know why cause it.
Can you help to explain the reason…
Hello experts,
In my project I need to write some bare metal code in order to boot my software (A VxWorks image), and would like to make the absolute minimum configurations before loading the VxWorks image, which then does the major part of the configurations…
Since ARM caches are physically indexed is there any way to flush based on the PA? I know I can get the set, but what about the way? If I am flushing from L1 would I have to flush all ways in L1 and then L2 assuming there is no L3 to get to system memory…
Hello,
I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9).
In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches, MMU and Program Prediction.
What I need is to know…
Hi All,
I am using Arm Cortex-A53 based board.I modified a driver module and the interrupt processing.
I have a fundamental question:
Since Arm Cortex-A53 can handle 16 primary interrupts, what happens if all the interrupts arrive at same time. Though…
I don't have much experience in building an embedded system from 0. I want to ask a general question as showed in the title through an example.
I choose Cortex-A9 (ARMv7-Profile A architecture) as CPU. Then I want to use DDR3 RAM of Alliance memory…
Hi,
The Cortex-A53 core supports either ACE or CHI as its master interface. Assuming I don't need any of the coherent features introduced in the ACE specification, is there any functional problem if Cortex-A53 ACE interface is connected to an AXI-4 interconnect…
Im new to ARM. Im learning generic timers in cortex a-53. I wanted to know whats the meaning of "system level implementation" of Generic Timer and "PE implementations" of the Generic Timer. How is it different from Generic timer…
Hello, sorry if i posted in the wrong forum.
I would like to know how memory mapping is done, that is to say which software/hardware component allow me to write for exemple into the address 0 of the flash memory in using the address 0x20000000 in my code…
I am timing load and store instructions for baremetal program by stepping though execution using OpenOCD and using the PMU cycle counter with single cycle granularity. I am running the program on a single core of a Cortex-A9 on a Xilinix Zynq-7000…
We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core.
While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly ordered (Device-nGnRnE memory type) and then witness…
excuse me for my English!!!
i want to write bare-metal startup code in 32-bit mode for LS1043A-Rdb.it is having V8 A53 core.
i have bare-metal 32bit(AARCH32) code for xilinx processor(which is of V8,A53core).How much of that code is useful to write code…
******************************************************************************/ /*****************************************************************************/ /** * @file translation_table.s * * @addtogroup a53_32_boot_code * @{ * <h2> translation_table…
hello guys, can you tell me the number of execution units in Cortex-A72 and the number of clock cycles it takes per instruction?
Thanks in advance
Folks,
I am trying to run linux 'perf' on a new board with 2 ARM cortex-a9 CPUs. After compiling the kernel to include perf tool, i run 'perf stat true' and it returns valid stats. But when I run 'perf record' to profile my program, it doesn't record…
can you please tell me how to boot up a processor in 32 bit mode for Armv8, A53 core using baremetal code?how can i know it is booted in 32bit mode?
Thanks.
Hello all,
The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC-DED) and for L1 D-cache dirty (which is SED-SEC) triggered…
hi,
on a cortex a53, I would like to get the best of both worlds. Having dcache enabled but no page walk in case of a miss.
I want no memory protection because we manage the whole system ( kind of baremetal processes)
Is there a way to tell the mmu controller…
From a previous question I got that setting the EPDx bits from the TCR_ELx register to 1 will disable table walk.
Good starting point. But, should I access the same memory location again, it won't be in the TLB cache.
How to work around that?
Where is the register definition of the CurrentEL register ?. I cannot seem to find it in the ARMv8A programming model guide or the Cortex-A53 TRM.
. How does the PSTATE bits map to CurrentEL ?
I read somewhere that a CurrentEL value of 0x4 denotes EL1…
ARMv8-A specification mentions revisions and options. I cannot find Cortex-A35 adheres to which exact version: ARMv8.1, 8.2, 8.3? I want to know which of the extensions described in the generic ARMv8-A spec are really available in that core.
Thanks…