• System wide cache flush

    Hello,

    I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system:

    My need is to flush a cached memory area to RAM in order to be viewed by the M4 core, unfortunately this area maybe cached by Core 0 and…

  • io coherency and shareability

    Hi,

    I have been reading about io coherency and the inner/outer shareability (SH bits in PTE). I kind of understand the concept of both but need help to connect the 2 concepts together. Lets assume a platform with (runs only one OS):

    - CCI-400
    - A53 Cluster…

  • What is difference between DCCIMVAC and DCIMVAC?

    The DCIMVAC represents a cache invalidate work. But one specific remark is that it will clean the data if the data is dirty before invalidation. Refer to followings

    /******************************************************/

    6.2.4 Data cache maintenance…

  • How to flush write buffer when memory attribute is normal_nc

    Hi,

    I am working on access pcie bar in armv8-a cpu(cortex-A5x) powered soc. Right now, I encounter an issue about (maybe) coherent issue.

    When I write data(4 bytes aligned) to pcie bar with ioremap_wc, there is some incorrect data. And it is correct…

  • Cache Coherence

    Hi ,

       I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid.

       1. Bring Core 1 out of reset.

       2. Bring Core 2 out of reset.

       3. Invalidate Core 2 data cache…

  • MOESI state encoding of Cortex-A7

    Hi,

    I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"

    we can see several information regarding a cache line. Those are:

    1. Current data in cache

    2. its 4-bit MOESI state,

    3. Outer Memory Attribute

    4. its tag

    5. NS State.

    However…

  • Cache cleaning and invalidating in ARM Cortex-A

    Cleaning or invalidating the L1 cache and L2 cache will not be a single atomic operation. A core might therefore perform cache maintenance on a particular address in both L1 and L2 caches only as two discrete steps. If another core were to access the…

  • Why A9 is multicore by A8 doesn't

    Hi Experts,

    Which factor in processor decides whether it can be used in multi-core or not ?

    Like as per my understanding A8 is used in single core whereas A9 is used in multi core. So which distinctive feature in A9 favors the multi core application ?

  • General Feature of Cortex processors on cache coherency

    Hi Experts,

    Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ?

    I found some features like CCI module available to provide this feature in multi-core environment. Other than that, is it possible…

  • VMSAv8-64 and spinlock

    Hi,

    I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache coherence.

    I'm writing bare-metal code, without…

  • shareability attribute for armv8 cortex a-53

    Hi,

    I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

    My question is how should I interpret the shareability domain: inner, outer…

  • ARMv7-A: Cache maintenance operation by VA, performance

    Hi,

    according to this talk, cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop to run over the entire memory block (in steps equal…

  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

    Hi, 

    I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

    The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

    There is no L3 cache. So the memory…

  • Is Cache Stashing introduced in DynamIQ similar to IO coherency?

     IO coherency also allows device to access coherent memory space. The only difference I noticed is that cache stashing connects device directly with cluster, however, IO coherency transactions need to go through system interconnect.

  • Cache and store buffer maintenance in cortex-a8!

    Dear All,

    Technical data sheets for the ARM7500FE  and ARM7100 say that:

    "In the ARM Processor the cache will be searched regardless of the state of the C bit, only reads that miss the cache will be affected."

    Now the question is that whether…

  • Cache maintenance and DMA

    Greetings ARM community,

    I have been tasked with cache maintenance.  The necessity popped up because of DMA issues on USB.

    As a quick (not perm solution) I used the invalidate all routine.  While obviously not nominal in anyway

    it does allow me…

  • What's the Cortex-A12 Main Bus Interface?

    Does Cortex-A12 not supprt AMBA4 ACE protocol?

    The figure and description of the Cortex-A12 product page(http://www.arm.com/products/processors/cortex-a/cortex-a12-processor.php) shows as if it only supports "AMBA4 AXI Bus" is available bus interface…