• Armv7 ICIALLU vs ICIALLUIS

    Hi experts! I have a question about cache instruction.

    DDI0406C_b_arm_architecture_reference_manual for Armv7  says

    Effect of the Multiprocessing Extensions on All and set/way maintenance operations

    The only architectural guarantee for the following…

  • ARM v8 PMU Cycle counter

    All,

    When I am using the cycle counter in AArch64, I am not getting cycles properly. I have enabled read of pmccntr_el0 in user space using a small kernel module. I have sample code like:

    asm volatile("isb;mrs %0, pmccntr_el0" : "=r"(prev));

    sleep…

  • Performance effect because of removing some instructions from ARMv8?

    I was going through the ARMv8 Architecture Reference Manual and I came to know that it does not support many instructions that were previously supported by ARMv7 architecture. For example ARMv8 does not support conditional codes and have a seperate instruction…

  • compiling kernel: -mcpu=cortex-a15 vs -march=armv7ve?

    I'm compiling an Android kernel for my Xperia Z using Linaro GCC 4.9. My question is, which option gives better optimization -mcpu=cortex-a15 or -march=armv7ve? Or do they give the same results?