• Arm Really Should Standardize An SMC Interface For Hardware Random Number Generators

    Intel and AMD have added RDRAND a long time ago. IBM added the (awesomely named) DARN instruction to POWER9.

    What do we have on AArch64? A mess. Ad-hoc drivers for specific RNGs, specified in device trees and (OMG) ACPI tables with device tree pieces…

  • Cannot access EL1 resources from EL3 or secure world on armv8.

    The working secerio is that I'm testing OP-TEE on a Hikey board(Cortex-A53, armv8), and they use arm-trusted-firmware(see https://github.com/linaro-swg/arm-trusted-firmware) to be the monitor running in EL3.

    I'm trying to access some resources in EL1…

  • Exceptions levels in the ARMv8 architecture

    Hello

    There are four exceptions levels in the ARMv8 architecture.

    EL0
    EL1
    EL2

    EL3

    Can anyone explain more of the EL3 execption level? What does it mean by 'allows swtiching between secure and nonsecure processor states? Secure monitor?

    Thanks

  • is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

    hi :

    I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).

    however, I can not find any clue about flushing L2 cache to DRAM(if without L3). 

    and I saw some points that L2 flushing was not needed.

    for ARMv8,  how can…

  • ARM Trusted Firmware, number of cpu cores..

    Hi all,

    I have two questions about ARM Trusted Firmware. I suppose that I already have answer for one of them..

    1. Does Trusted Operating System (at Secure EL1) use or can use, more than one cpu core, or it always executes on one core?
    2. Does bl31, runtime firmware…

  • Launching bare-metal firmware at EL2 (Hyp) on QEMU with ARM Trusted Firmware?

    Hi experts,

    I am recently developing some bare-metal code for a Cortex-A57 Aarch64 on QEMU (Virt platform) for playing with the Virtualization Extension. I first used one core and I developed a bootloader from scratch that switches the execution from…