AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

In AXI, low-power mode uses CSYSREQ, CSYSACK and CACTIVE three signal to realize the function, but I think only CSYSREQ and CACTIVE can realize the fuctionk, CSYSACK seems to be unnecessary?

AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

As usual, we talk about cache is mainly refer to the cache inside CPU, but AXI's cache or buffer…

In document on AXI3:

"The exclusive access monitor records the address and ARID value of any exclusive read

operation. Then it monitors that location until either a write occurs to that location or

until another exclusive read with the same ARID value…

1/ What will happen when a master performs 2 exclusive read with 2 different transaction ID to the sam an address location??

Example: Master0 (M0) issue 2 exclusive read with 2 different transaction ID (first is 00 and second is 01) to the sam an address…

In the document AMBA3 AXI (3.2 Relationships between the channels)

     Two relationships that must be maintained are:

          • read data must always follow the address to which the data relates…

1/ WHY "the width of the ID field at a slave interface is wider than the ID field at a master

interface"??? Can you please explain in more detail the reason???

2/ Do AXI protocol have support "read interleaving"???

Thanks you so much…

I am a junior ASIC engineer. At the moment, I have three the question about AMBA AXI 3.0

1. No combination paths between master and slave, all timing path must be registered. Why the VALID and READY signals can assert in the same time ?

2. In the FIXED…

Hi guys,

I have two questions related to the write-strobing in AXI4. Both examples work on a 32-bit bus.

First consider an unaligned access on address 0x1.

Can this access be created in 2 ways?

1) Addr=0x0, Wrstrb=1110

2) Addr=0x1, Wrstrb=0111

In the second…

Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.

as you can see the first picture, slave send the read…

I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.

i wonder about interleaving and out-of order.

AXI supports…

Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

Recently, I read "AMBA AXI Protocol.pdf". but i have two questions about AXI after reading.

Firstly, i very wonder AWID, WID and BID when write transaction…

Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.

firstly, i very wonder the handshake…

Hi AXI-experts,

Does AX4 support burst sizes larger than the bus width?

Narrow transactions are allowed, but do wider transactions also work?

Best regards,

Robert

I have bunch of questions related to AXI. Can someone help me by answering those?

AxSize can be varied across multiple transactions?

whose duty is to set byte strobe in a transfer? Is it the master which should generate byte strobes along with un-aligned…

Can someone explain me the advantage of having decouple write address, data channels in AXI4?

In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled…

HI,

Does anyone know the minimum number of error responce (wready & rvalid) when AxLEN = 15?

Does it need to respond 16th? or we can respond 1 only?

Regards,

-GARO

For any burst transfer Master has to pass only first address, for the consecutive transfer address calculation is taken care by Slave. So i want to know what is the basic difference in FIXED and INCR burst transfer?

I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed?

For example the master device will wait ARREADY assert or ARVALID dessert, before assert the RREADY?

Remark:

Just now, I noticed that…

In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are issued?

In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are issued?

Hi experts,

I get the following information about NSAID from TZC-400 trm.
The Non-Secure Access IDentity (NSAID) input identifies the source interface of a transaction to a filter unit.
When in Non-secure state the NSAID inputs identify the master that…

Hello,

       I have a question regarding the AXI protocol, which I can seem to find the answer from the spec.

       On the AXI read bus.

       If the master send the slave 10 read burst commands…

1. I'm examining AXI burst of FIXED type.

2. Data bus width is of 128bit.

3. case scenario WRITE:

    awlen    = 2 (3 write transfers)

    awsize  = 2 (32bit per each transfer)

    awburst = 0 (FIXED)…

Hello,

Regarding AXI WR transaction.

I'm interested to know what happens if on an AXI write transaction, the WR data channel put the channel info before the address channel info is valid.

This means that in order to complete the transaction, sometimes…