• AXI4: Write-Alignemnent modes? Partial writing with write strobes possible?

    Hi guys,

    I have two questions related to the write-strobing in AXI4. Both examples work on a 32-bit bus.

    First consider an unaligned access on address 0x1.

    Can this access be created in 2 ways?

    1) Addr=0x0, Wrstrb=1110

    2) Addr=0x1, Wrstrb=0111

    In the second…

  • Supported AXI transfers on Cortex-A9?

    Hi folks,

    The technical reference states that only a subset of possible AXI transactions are actually generated.

    This is described in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Babiaggf.html

    What happens for this table if the master…