Hi everyone! Please help me.. i have  a project with a custom axi slave  design that  implements multiple memory ranges 256 words each . A master ( my processor in figure) can write burst data to the example slave and read the data back. The problem is…

Hi,

I am experiencing A complete arm core hang when both of the cores are employed in SMP mode and using DMA.

I was tested with Linux kernels 3.10, 4.1 and 4.6 in SMP mode.

SOC used is Altera Cyclone V SOC-FPGA with dual Cortex A9.

The DMA transfer goes from…

Hi experts,

I would like to know more about the interconnection between Cortex-A9 and the PL310 L2 cache controller.

I think Figure 1.2 in the TRM is a good starting point:

CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual: 1.2. Typical…