Hi everyone! Please help me.. i have  a project with a custom axi slave  design that  implements multiple memory ranges 256 words each . A master ( my processor in figure) can write burst data to the example slave and read the data back. The problem is…

Hi,

  What is real time application of AXI exclusive access.

  Is it necessarily to do Exclusive read first then exclusive write.

  May i know the reason is it so?

Hi experts,

I would like to know more about the interconnection between Cortex-A9 and the PL310 L2 cache controller.

I think Figure 1.2 in the TRM is a good starting point:

CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual: 1.2. Typical…

Hello,

I am working on Cortex-A53  and using Cortex-A53 DSM Model in my design. We are getting Data Abort exception on a read to ROM address and ESR_EL3 register showing its a DECERR External error. MMU and Cache both are not enabled at this point where…

hey,

How to modify the value of AWCACHE [3:0] and ARCACHE[3:0] in AXI?

in baremental driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x00,

but in linux driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x01,

can anybody tell me…

Hi,

I am experiencing A complete arm core hang when both of the cores are employed in SMP mode and using DMA.

I was tested with Linux kernels 3.10, 4.1 and 4.6 in SMP mode.

SOC used is Altera Cyclone V SOC-FPGA with dual Cortex A9.

The DMA transfer goes from…

Hello,

I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I  the system there will be a cortex A7 master(64bytes cache line). My question is: in case of such transaction (WriteLineUnique with 128bytes…