• Write interleaving with Multi-AXI master

    Hi,

    I have multiple questions related to multi-master AXI4 system. Eg: lets say we have 2 masters(m1,m2) and 2 slaves(s1,s2) and an interconnect.

    1) In parallel, Can i have transfers(burst) to m1->s1, m2->s2 on write data channels? A-data form M1,  B-data…

  • Support for pipelining flops in AXI

    Hi All,

    Does ARM support pipelining flops in between valid/ready signals?Can someone explain why its *not* possible?

    Thanks

  • AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

    AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

  • AXI4: Write-Alignemnent modes? Partial writing with write strobes possible?

    Hi guys,

    I have two questions related to the write-strobing in AXI4. Both examples work on a 32-bit bus.

    First consider an unaligned access on address 0x1.

    Can this access be created in 2 ways?

    1) Addr=0x0, Wrstrb=1110

    2) Addr=0x1, Wrstrb=0111

    In the second…

  • AXI4: Wider transactions than BUS width allowed?

    Hi AXI-experts,

    Does AX4 support burst sizes larger than the bus width?

    Narrow transactions are allowed, but do wider transactions also work?

    Best regards,

    Robert

  • Questions on AXI4

    I have bunch of questions related to AXI. Can someone help me by answering those?

    AxSize can be varied across multiple transactions?

    whose duty is to set byte strobe in a transfer? Is it the master which should generate byte strobes along with un-aligned…

  • Reason for having decouple write address, data channels in AXI4

    Can someone explain me the advantage of having decouple write address, data channels in AXI4?

    In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled…

  • About AXI4 address channel and data channel handshake sequence

    I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed?

    For example the master device will wait ARREADY assert or ARVALID dessert, before assert the RREADY?

    Remark:

    Just now, I noticed that…

  • MakeUnique Transaction (ACE protocol)

    Hi.,

    As we know that there is a MakeUnique transaction in ace protocol, can anyone tell me how we can initiate this transaction..? I mean what is the respective signal in AXI4/ACE that allows us to set a master to initiate this MakeUnique transaction.…

  • Are there any restrictions for the width of an address signal in an AXI4 interface?

    Hello,

    in the AXI4 specification I didn't find anything mentioned about width restrictions for the address signal. I'm currently trying to simulate a component which I wrote in VHDL which provides an AXI4 Slave interface. The BFM I'm using to simulate…

  • AXI Write data interleaving

    Hello Everyone,

    [This not specific to AXI3/4] Can someone give an example on how write data interleaving works? Is it used only when we have multi-master cases? or its possible with single-master cases also?

    In case if we have 2 burst transfers with A …

  • Address handshaking in AXI4

    Hi  there,

    I have question regarding handshaking in the AXI protocol.Currently i am designing  decorder for AXI4-Lite master .

    While doing the write adress  transaction, AWVALID  depends upon write enable.AWVALID is high when write enable signal…

  • In read or write transaction in AXI.what happen if data transaction  is before address.

    HI there,

    I have question regarding transaction in AXI4 bus (or any other bus). What happens  in write any read action when data transaction (handshaking) occurs before  address  transaction (handshaking) ?

    Will the data be written to the…