1/ What will happen when a master performs 2 exclusive read with 2 different transaction ID to the sam an address location??

Example: Master0 (M0) issue 2 exclusive read with 2 different transaction ID (first is 00 and second is 01) to the sam an address…

In the document AMBA3 AXI (3.2 Relationships between the channels)

     Two relationships that must be maintained are:

          • read data must always follow the address to which the data relates…

1/ WHY "the width of the ID field at a slave interface is wider than the ID field at a master

interface"??? Can you please explain in more detail the reason???

2/ Do AXI protocol have support "read interleaving"???

Thanks you so much…

Hello everyone,

Please describe me the transfer continuation process after ERROR response from the slave.

As shown in the above figure at cycle T4 if MASTER identifies the ERROR response from the SLAVE. Now, if the MASTER wants to continue the current transfer…

I am a junior ASIC engineer. At the moment, I have three the question about AMBA AXI 3.0

1. No combination paths between master and slave, all timing path must be registered. Why the VALID and READY signals can assert in the same time ?

2. In the FIXED…

Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.

as you can see the first picture, slave send the read…

I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.

i wonder about interleaving and out-of order.

AXI supports…

Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

Recently, I read "AMBA AXI Protocol.pdf". but i have two questions about AXI after reading.

Firstly, i very wonder AWID, WID and BID when write transaction…

Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.

firstly, i very wonder the handshake…

Hi guys,

I'm new to the AXI ecosystem.

However, I have one question related to unaligned read transfers.

Does AXI4 support unaligned read transfers although er are no strobe lines?

If so, which data on the bus is written?

To make it easier, discuss it…

Can someone explain me the advantage of having decouple write address, data channels in AXI4?

In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled…

HI,

Does anyone know the minimum number of error responce (wready & rvalid) when AxLEN = 15?

Does it need to respond 16th? or we can respond 1 only?

Regards,

-GARO

Does anyone know of an Idiot's Guide to this topic? In particular, how does a processor with no special I/O instructions issue a request, e.g. to a serial output device to output "Hello, World"? And how does Memory-Mapped I/O work in detail? Where is…

I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed?

For example the master device will wait ARREADY assert or ARVALID dessert, before assert the RREADY?

Remark:

Just now, I noticed that…

The spec simply states that a master may cancel a burst after receiving an ERROR response for one of its transfers or continue with the remaining transfers.

The spec does not go on to state what the slave is supposed to do in that case though. Should it…

In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are issued?

Hello,

i have the Zedboard which contains arm Cortex-A9 cortex with the amba bus..

i have searched a lot but I probaly miss the point.

i want to use data and to transfer  data from the processing system to the programable logic section via the amba bus…

Hi,

    i am confusing in the following point ,with an example....

   if

     Start_Address = 23

     Number_Bytes = 8

     Burst_Length   = 8

     data_Bus_Byte…

Hi,

My question is about duration of hsel in AHB. While performing a write operation to a particular slave, if hsel for the slave is asserted (hsel=1) in the address
face and is deasserted (hsel=0) in the data phase, will it guarantee that data is written…

1. I'm examining AXI burst of FIXED type.

2. Data bus width is of 128bit.

3. case scenario WRITE:

    awlen    = 2 (3 write transfers)

    awsize  = 2 (32bit per each transfer)

    awburst = 0 (FIXED)…

Hi.,

As we know that there is a MakeUnique transaction in ace protocol, can anyone tell me how we can initiate this transaction..? I mean what is the respective signal in AXI4/ACE that allows us to set a master to initiate this MakeUnique transaction.…

I'm trying to understand the write strobe functionality for a 128bit bus width, burst type FIXED.

Case scenario:

AXI bus width 128bit.

awlen    = 3 (4 write transfers)

awsize  = 2 (32bit per each transfer)

awburst = 0 (FIXED)

awaddr…

Hello,

in the AXI4 specification I didn't find anything mentioned about width restrictions for the address signal. I'm currently trying to simulate a component which I wrote in VHDL which provides an AXI4 Slave interface. The BFM I'm using to simulate…

Hi,

Can I get reference document for  AMBA 5 CHI specification.? Please Can anyone share me that doc...?

Thanks & Regards,

Rakesh Reddy.B

Hello Everyone,

Can someone explain the use cases of AxPROT? I am not fully clear on how to use these bits in a system. (So i would like to hear some use cases for this port)

Also, Please provide some info on how to set AxPROT[1] (How the system will distinguish…