Hello,

i have the Zedboard which contains arm Cortex-A9 cortex with the amba bus..

i have searched a lot but I probaly miss the point.

i want to use data and to transfer  data from the processing system to the programable logic section via the amba bus…

Hello,

I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I  the system there will be a cortex A7 master(64bytes cache line). My question is: in case of such transaction (WriteLineUnique with 128bytes…

Hi Experts,

Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ?

I found some features like CCI module available to provide this feature in multi-core environment. Other than that, is it possible…