• Cache type and cache operation sequence

    I have a shared memory in DDR  --- shared between two separate ARM execution environments (say A and B)  in a heterogeneous compute SoC.

    SW on each execution units (A and B) Reads and Writes to this shared location (imagine a array/matrix that…

  • pl310 CACHE_ID register

    In the PL310 TRM, the definition of the CACHE_ID register define the RTL release as the lower bits of the register.

    To translate this RTL to a revision information, it is stated that

    "RTL release 0x9 denotes r3p3 code of the cache controller. See the Release…

  • AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

    AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

    As usual, we talk about cache is mainly refer to the cache inside CPU, but AXI's cache or buffer…