• 4-kbyte boundary space

    Note: This was originally posted on 22nd August 2012 at http://forums.arm.com

    Hi there,
    when I read AMBA AXI4 specification, the spec shows that "Bursts must not cross 4KB boundaries to prevent them from crossing boundaries between slaves and to limit the…

  • AXI4: Wider transactions than BUS width allowed?

    Hi AXI-experts,

    Does AX4 support burst sizes larger than the bus width?

    Narrow transactions are allowed, but do wider transactions also work?

    Best regards,

    Robert

  • ACE-Lite Master and Slaves

    Hello Ashley,

          I have couple of basic doubts w.r.t ACE-Lite Slave.

          The AMBA spec for ACE-Lite says that " ACE-Lite is used by master components that do not have hardware coherent caches". But they can issue transactions…

  • Problems with  AXI4  write data channel

    Hello:

        Suppose there are 2 masters(master0 and master1) and 2 slaves(slave0 and slave1) for AXI4. As AXI4 protocol has removed WID signal for write data channel，When slave0 has received wvaild which is pulled up afte  slave0 has…

  • AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

    AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

  • AXI4: Unaligned read transactions

    Hi guys,

    I'm new to the AXI ecosystem.

    However, I have one question related to unaligned read transfers.


    Does AXI4 support unaligned read transfers although er are no strobe lines?

    If so, which data on the bus is written?

    To make it easier, discuss it…

  • Reason for having decouple write address, data channels in AXI4

    Can someone explain me the advantage of having decouple write address, data channels in AXI4?

    In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled…

  • About AXI4 address channel and data channel handshake sequence

    I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed?

    For example the master device will wait ARREADY assert or ARVALID dessert, before assert the RREADY?

    Remark:

    Just now, I noticed that…

  • MakeUnique Transaction (ACE protocol)

    Hi.,

    As we know that there is a MakeUnique transaction in ace protocol, can anyone tell me how we can initiate this transaction..? I mean what is the respective signal in AXI4/ACE that allows us to set a master to initiate this MakeUnique transaction.…

  • Are there any restrictions for the width of an address signal in an AXI4 interface?

    Hello,

    in the AXI4 specification I didn't find anything mentioned about width restrictions for the address signal. I'm currently trying to simulate a component which I wrote in VHDL which provides an AXI4 Slave interface. The BFM I'm using to simulate…

  • Need info AXI4- AxPROT

    Hello Everyone,

    Can someone explain the use cases of AxPROT? I am not fully clear on how to use these bits in a system. (So i would like to hear some use cases for this port)

    Also, Please provide some info on how to set AxPROT[1] (How the system will distinguish…

  • Address decoding in AXI4 interconnect

    Hi, anybody explain how data  is routed in interconnect? As stated in AXI4 spec, only start address issued from master,then how it is done in case of burst transaction? Please Explain how this is done.

  • In read or write transaction in AXI.what happen if data transaction  is before address.

    HI there,

    I have question regarding transaction in AXI4 bus (or any other bus). What happens  in write any read action when data transaction (handshaking) occurs before  address  transaction (handshaking) ?

    Will the data be written to the…

  • Does an AXI4 master have to assert the correct WSTRB for unaligned transfers?

    Take the unaligned transfer on page A3-55 in the "AMBA AXI and ACE Protocol Specification" with address 0x07 as example.

    Bus width and data transfer width should be both 32 bits. First write should be to address 0x07. This would lead to bytes…